Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 20 of 20) sorted by relevance

/hal_nordic-latest/nrfx/hal/
Dnrf_vpr_csr.h419 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT); in nrf_vpr_csr_machine_cycle_counter_enable_set() local
421 reg = (reg & ~VPRCSR_MCOUNTINHIBIT_CY_Msk) | (enable ? in nrf_vpr_csr_machine_cycle_counter_enable_set()
425 nrf_csr_write(VPRCSR_MCOUNTINHIBIT, reg); in nrf_vpr_csr_machine_cycle_counter_enable_set()
430 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT); in nrf_vpr_csr_machine_cycle_counter_enable_check() local
432 return (reg & (VPRCSR_MCOUNTINHIBIT_CY_INHIBIT << VPRCSR_MCOUNTINHIBIT_CY_Pos)) ? false : true; in nrf_vpr_csr_machine_cycle_counter_enable_check()
442 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT); in nrf_vpr_csr_machine_instruction_counter_enable_set() local
444 reg = (reg & ~VPRCSR_MCOUNTINHIBIT_IR_Msk) | (enable ? in nrf_vpr_csr_machine_instruction_counter_enable_set()
448 nrf_csr_write(VPRCSR_MCOUNTINHIBIT, reg); in nrf_vpr_csr_machine_instruction_counter_enable_set()
453 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT); in nrf_vpr_csr_machine_instruction_counter_enable_check() local
455 return (reg & (VPRCSR_MCOUNTINHIBIT_IR_INHIBIT << VPRCSR_MCOUNTINHIBIT_IR_Pos)) ? false : true; in nrf_vpr_csr_machine_instruction_counter_enable_check()
[all …]
Dnrf_gpio.h987 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_cfg() local
988 uint32_t cnf = reg->PIN_CNF[pin_number]; in nrf_gpio_cfg()
1013 reg->PIN_CNF[pin_number] = cnf; in nrf_gpio_cfg()
1023 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_reconfigure() local
1024 uint32_t cnf = reg->PIN_CNF[pin_number]; in nrf_gpio_reconfigure()
1047 reg->PIN_CNF[pin_number] = cnf; in nrf_gpio_reconfigure()
1165 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_pin_dir_set() local
1166 reg->DIRSET = (1UL << pin_number); in nrf_gpio_pin_dir_set()
1173 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_pin_set() local
1175 nrf_gpio_port_out_set(reg, 1UL << pin_number); in nrf_gpio_pin_set()
[all …]
Dnrf_vpr_csr_vio.h877 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_OUTMODE); in nrf_vpr_csr_vio_mode_out_get() local
879 p_mode->mode = (nrf_vpr_csr_vio_shift_t)((reg & VPRCSR_NORDIC_OUTMODE_MODE_Msk) in nrf_vpr_csr_vio_mode_out_get()
881 p_mode->frame_width = (reg & VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Msk) in nrf_vpr_csr_vio_mode_out_get()
887 uint32_t reg = ((uint32_t)p_mode->mode << VPRCSR_NORDIC_OUTMODE_MODE_Pos) | in nrf_vpr_csr_vio_mode_out_set() local
891 nrf_csr_write(VPRCSR_NORDIC_OUTMODE, reg); in nrf_vpr_csr_vio_mode_out_set()
896 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_OUTMODEB); in nrf_vpr_csr_vio_mode_out_buffered_get() local
898 p_mode->mode = (nrf_vpr_csr_vio_shift_t)((reg & VPRCSR_NORDIC_OUTMODEB_MODE_Msk) in nrf_vpr_csr_vio_mode_out_buffered_get()
900 p_mode->frame_width = (reg & VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Msk) in nrf_vpr_csr_vio_mode_out_buffered_get()
907 uint32_t reg = ((uint32_t)p_mode->mode << VPRCSR_NORDIC_OUTMODEB_MODE_Pos) | in nrf_vpr_csr_vio_mode_out_buffered_set() local
911 nrf_csr_write(VPRCSR_NORDIC_OUTMODE, reg); in nrf_vpr_csr_vio_mode_out_buffered_set()
[all …]
Dnrf_vpr_csr_vtim.h272 uint32_t reg; in nrf_vpr_csr_vtim_simple_counter_top_set() local
277 reg = nrf_csr_read(VPRCSR_NORDIC_CNTTOP); in nrf_vpr_csr_vtim_simple_counter_top_set()
278 reg &= ~VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk; in nrf_vpr_csr_vtim_simple_counter_top_set()
279 reg |= value << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos; in nrf_vpr_csr_vtim_simple_counter_top_set()
280 nrf_csr_write(VPRCSR_NORDIC_CNTTOP, reg); in nrf_vpr_csr_vtim_simple_counter_top_set()
283 reg = nrf_csr_read(VPRCSR_NORDIC_CNTTOP); in nrf_vpr_csr_vtim_simple_counter_top_set()
284 reg &= ~VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk; in nrf_vpr_csr_vtim_simple_counter_top_set()
285 reg |= value << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos; in nrf_vpr_csr_vtim_simple_counter_top_set()
286 nrf_csr_write(VPRCSR_NORDIC_CNTTOP, reg); in nrf_vpr_csr_vtim_simple_counter_top_set()
Dnrf_hsfll.h409 uint32_t reg = p_reg->CLOCKSTATUS; in nrf_hsfll_status_clk_get() local
412 (nrf_hsfll_mode_status_t)((reg & HSFLL_CLOCKSTATUS_MODE_Msk) >> HSFLL_CLOCKSTATUS_MODE_Pos); in nrf_hsfll_status_clk_get()
413 p_status->override = ((reg & HSFLL_CLOCKSTATUS_OVERRIDE_Msk) in nrf_hsfll_status_clk_get()
416 p_status->accuracy = ((reg & HSFLL_CLOCKSTATUS_ACCURACY_Msk) in nrf_hsfll_status_clk_get()
419 p_status->locked = ((reg & HSFLL_CLOCKSTATUS_LOCKED_Msk) in nrf_hsfll_status_clk_get()
467 uint32_t reg = p_reg->CLOCKCTRL.MODE; in nrf_hsfll_clkctrl_mode_get() local
470 (nrf_hsfll_mode_ctrl_t)((reg & HSFLL_CLOCKCTRL_MODE_MODE_Msk) in nrf_hsfll_clkctrl_mode_get()
472 p_clkctrl->override = ((reg & HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk) in nrf_hsfll_clkctrl_mode_get()
Dnrf_qspi.h954 uint32_t reg = 0; in nrf_qspi_cinstrdata_set() local
961 reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos; in nrf_qspi_cinstrdata_set()
964 reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos; in nrf_qspi_cinstrdata_set()
967 reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos; in nrf_qspi_cinstrdata_set()
970 reg |= ((uint32_t)p_tx_data_8[4]); in nrf_qspi_cinstrdata_set()
971 p_reg->CINSTRDAT1 = reg; in nrf_qspi_cinstrdata_set()
972 reg = 0; in nrf_qspi_cinstrdata_set()
975 reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos; in nrf_qspi_cinstrdata_set()
978 reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos; in nrf_qspi_cinstrdata_set()
981 reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos; in nrf_qspi_cinstrdata_set()
[all …]
Dnrf_auxpll.h482 uint32_t reg = p_reg->CONFIG.CFGSTATIC; in nrf_auxpll_config_get() local
485 (reg & AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Msk) >> AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Pos; in nrf_auxpll_config_get()
488 … (reg & AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Pos; in nrf_auxpll_config_get()
491 (reg & AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Pos; in nrf_auxpll_config_get()
494 … (reg & AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Pos; in nrf_auxpll_config_get()
496 p_cfg->range = (nrf_auxpll_divider_range_t)((reg & AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Msk) in nrf_auxpll_config_get()
Dnrf_tampc.h1741 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type * reg = in nrf_tampc_protector_ctrl_value_set() local
1745 reg->CTRL = (TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear in nrf_tampc_protector_ctrl_value_set()
1748 reg->CTRL = ((reg->CTRL & ~TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk) | in nrf_tampc_protector_ctrl_value_set()
1758 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const * reg = in nrf_tampc_protector_ctrl_value_get() local
1761 return ((reg->CTRL & TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk) in nrf_tampc_protector_ctrl_value_get()
1770 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type * reg = in nrf_tampc_protector_ctrl_lock_set() local
1774 reg->CTRL = (TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear in nrf_tampc_protector_ctrl_lock_set()
1777 reg->CTRL = ((reg->CTRL & ~TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk) | in nrf_tampc_protector_ctrl_lock_set()
1787 NRF_TAMPC_PROTECT_ACTIVESHIELD_Type const * reg = in nrf_tampc_protector_ctrl_lock_get() local
1790 return ((reg->CTRL & TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk) in nrf_tampc_protector_ctrl_lock_get()
[all …]
Dnrf_uicr.h764 uint32_t reg = p_reg->BOOTCONF; in nrf_uicr_boot_region_config_get() local
765 p_config->permissions = reg & NRF_UICR_BOOTCONF_PERM_MASK; in nrf_uicr_boot_region_config_get()
766 p_config->writeonce = ((reg & UICR_BOOTCONF_WRITEONCE_Msk) >> UICR_BOOTCONF_WRITEONCE_Pos) == in nrf_uicr_boot_region_config_get()
768 p_config->lock = ((reg & UICR_BOOTCONF_LOCK_Msk) >> UICR_BOOTCONF_LOCK_Pos) == in nrf_uicr_boot_region_config_get()
770 p_config->size_kb = (reg & UICR_BOOTCONF_SIZE_Msk) >> UICR_BOOTCONF_SIZE_Pos; in nrf_uicr_boot_region_config_get()
771 return (reg != UICR_BOOTCONF_ResetValue); in nrf_uicr_boot_region_config_get()
Dnrf_rramc.h725 uint32_t reg = p_reg->REGION[region].CONFIG; in nrf_rramc_region_config_get() local
726 p_config->permissions = reg & NRF_RRAMC_REGION_CONFIG_PERM_MASK; in nrf_rramc_region_config_get()
727 p_config->writeonce = ((reg & RRAMC_REGION_CONFIG_WRITEONCE_Msk) in nrf_rramc_region_config_get()
730 p_config->lock = ((reg & RRAMC_REGION_CONFIG_LOCK_Msk) in nrf_rramc_region_config_get()
732 p_config->size_kb = (reg & RRAMC_REGION_CONFIG_SIZE_Msk) >> RRAMC_REGION_CONFIG_SIZE_Pos; in nrf_rramc_region_config_get()
Dnrf_cache.h738 volatile CACHEDATA_SET_WAY_Type const * reg = &p_reg->SET[set].WAY[way]; in nrf_cache_data_get()
741 case 0: return reg->DATA0; in nrf_cache_data_get()
742 case 1: return reg->DATA1; in nrf_cache_data_get()
743 case 2: return reg->DATA2; in nrf_cache_data_get()
744 case 3: return reg->DATA3; in nrf_cache_data_get()
/hal_nordic-latest/nrfs/src/services/
Dnrfs_diag.c43 req.reg.access_type = DIAG_REG_READ; in nrfs_diag_reg_read()
44 req.reg.addr = addr; in nrfs_diag_reg_read()
45 req.reg.val = 0; in nrfs_diag_reg_read()
60 req.reg.access_type = DIAG_REG_WRITE; in nrfs_diag_reg_write()
61 req.reg.addr = addr; in nrfs_diag_reg_write()
62 req.reg.val = val; in nrfs_diag_reg_write()
85 evt.reg.addr = p_rsp->data.addr; in nrfs_diag_service_notify()
86 evt.reg.val = p_rsp->data.val; in nrfs_diag_service_notify()
87 evt.reg.access_type = p_rsp->data.access_type; in nrfs_diag_service_notify()
Dnrfs_pmic.c273 req.reg.access_type = PMIC_REG_READ; in nrfs_pmic_test_if_read()
274 req.reg.addr = addr; in nrfs_pmic_test_if_read()
275 req.reg.val = 0; in nrfs_pmic_test_if_read()
290 req.reg.access_type = PMIC_REG_WRITE; in nrfs_pmic_test_if_write()
291 req.reg.addr = addr; in nrfs_pmic_test_if_write()
292 req.reg.val = val; in nrfs_pmic_test_if_write()
/hal_nordic-latest/drivers/nrf_802154/sl/sl_opensource/src/
Dnrf_802154_sl_fem.c58 nrf_radio_txpower_t reg; member
250 return to_radio_tx_power_convert(req_radio_power).reg; in mpsl_tx_power_dbm_to_radio_register_convert()
/hal_nordic-latest/nrfs/include/internal/services/
Dnrfs_diag.h41 diag_reg_access_t reg; /**< Register access. */ member
Dnrfs_pmic.h122 pmic_reg_access_t reg; /**< PMIC register access. */ member
/hal_nordic-latest/nrfs/include/services/
Dnrfs_diag.h30 } reg; /** Register request. */ member
/hal_nordic-latest/nrfx/samples/doc/buildfiles/
Dextra_stylesheet.css412 /* fix placement of <sup>&reg;</sup> */
/hal_nordic-latest/nrfx/doc/buildfiles/
Dextra_stylesheet.css416 /* fix placement of <sup>&reg;</sup> */
/hal_nordic-latest/drivers/nrf_802154/driver/src/
Dnrf_802154_trx.c302 uint32_t reg = mpsl_tx_power_dbm_to_radio_register_convert(txpower); in txpower_set() local
304 nrf_radio_txpower_set(NRF_RADIO, reg); in txpower_set()