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Searched refs:NRFX_ASSERT (Results 1 – 25 of 123) sorted by relevance

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/hal_nordic-3.6.0/nrfx/hal/
Dnrf_spu.h874 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk)); in nrf_spu_dppi_config_set()
889 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk)); in nrf_spu_gpio_config_set()
905 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk)); in nrf_spu_flashnsc_set()
906 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk)); in nrf_spu_flashnsc_set()
920 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk)); in nrf_spu_ramnsc_set()
921 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk)); in nrf_spu_ramnsc_set()
935 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk)); in nrf_spu_flashregion_set()
948 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk)); in nrf_spu_ramregion_set()
961 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk); in nrf_spu_peripheral_set()
962 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk)); in nrf_spu_peripheral_set()
[all …]
Dnrf_uicr.h348 NRFX_ASSERT(index < NRF_UICR_MEM_COUNT); in nrf_uicr_mem_config_get()
367 NRFX_ASSERT(index < NRF_UICR_MEM_COUNT); in nrf_uicr_mem_size_get()
374 NRFX_ASSERT(index < NRF_UICR_PERIPH_COUNT); in nrf_uicr_periph_config_get()
400 NRFX_ASSERT(index < NRF_UICR_GPIO_COUNT); in nrf_uicr_feature_own_get()
405 NRFX_ASSERT(index < NRF_UICR_GPIOTE_CH_COUNT); in nrf_uicr_feature_own_get()
409 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT); in nrf_uicr_feature_own_get()
413 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT); in nrf_uicr_feature_own_get()
417 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT); in nrf_uicr_feature_own_get()
421 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT); in nrf_uicr_feature_own_get()
428 NRFX_ASSERT(false); in nrf_uicr_feature_own_get()
[all …]
Dnrf_mpc.h714 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_config_set()
715 NRFX_ASSERT(p_config != NULL); in nrf_mpc_region_config_set()
738 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_config_get()
766 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_startaddr_set()
767 NRFX_ASSERT((address & 0xFFFUL) == 0); in nrf_mpc_region_startaddr_set()
774 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_startaddr_get()
783 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_addrmask_set()
784 NRFX_ASSERT((address & 0xFFFUL) == 0); in nrf_mpc_region_addrmask_set()
791 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_addrmask_get()
800 NRFX_ASSERT(index < NRF_MPC_REGION_COUNT); in nrf_mpc_region_masterport_set()
[all …]
Dnrf_vpr_clic.h214 NRFX_ASSERT(p_config); in nrf_vpr_clic_config_get()
226 NRFX_ASSERT(p_info); in nrf_vpr_clic_info_get()
239 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_pending_set()
246 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_pending_clear()
253 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_pending_check()
264 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_enable_set()
273 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_enable_check()
283 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_priority_set()
285 NRFX_ASSERT(priority < VPR_CLIC_PRIO_COUNT); in nrf_vpr_clic_int_priority_set()
296 NRFX_ASSERT(irq_num < NRF_VPR_CLIC_IRQ_COUNT); in nrf_vpr_clic_int_priority_get()
[all …]
Dnrf_memconf.h314 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_control_enable_set()
315 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_CONTROL_COUNT); in nrf_memconf_ramblock_control_enable_set()
330 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_control_mask_enable_set()
346 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_control_enable_check()
347 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_CONTROL_COUNT); in nrf_memconf_ramblock_control_enable_check()
357 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_ret_enable_set()
358 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET_COUNT); in nrf_memconf_ramblock_ret_enable_set()
372 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_ret_mask_enable_set()
388 NRFX_ASSERT(power_id < NRF_MEMCONF_POWERBLOCK_COUNT); in nrf_memconf_ramblock_ret_enable_check()
389 NRFX_ASSERT(ramblock <= NRF_MEMCONF_POWERBLOCK_RAMBLOCK_RET_COUNT); in nrf_memconf_ramblock_ret_enable_check()
[all …]
Dnrf_exmif.h176 NRFX_ASSERT(p_device->size <= NRF_EXMIF_MAX_MEMORY_DEVICE_SIZE); in nrf_exmif_device_config()
177 NRFX_ASSERT(device_idx < NRF_EXMIF_MAX_NUMBER_OF_DEVICES); in nrf_exmif_device_config()
189 NRFX_ASSERT(false); in nrf_exmif_device_config()
197 NRFX_ASSERT(device_idx < NRF_EXMIF_MAX_NUMBER_OF_DEVICES); in nrf_exmif_device_enable()
207 NRFX_ASSERT(false); in nrf_exmif_device_enable()
215 NRFX_ASSERT(device_idx < NRF_EXMIF_MAX_NUMBER_OF_DEVICES); in nrf_exmif_device_disable()
225 NRFX_ASSERT(false); in nrf_exmif_device_disable()
/hal_nordic-3.6.0/nrfx/helpers/
Dnrfx_gppi_dppi_ppib.c65 NRFX_ASSERT(p_path); in path_cleanup()
74 NRFX_ASSERT(p_allocated_channels); in channel_free()
86 NRFX_ASSERT(p_channel); in channel_allocate()
132 NRFX_ASSERT(p_src_apb != p_dst_apb); in apb_connection_remove()
133 NRFX_ASSERT(p_src_apb); in apb_connection_remove()
134 NRFX_ASSERT(p_dst_apb); in apb_connection_remove()
135 NRFX_ASSERT(nrfx_interconnect_apb_domain_get(p_src_apb) == in apb_connection_remove()
137 NRFX_ASSERT(nrfx_interconnect_apb_domain_get(p_src_apb) == NRF_DOMAIN); in apb_connection_remove()
150 NRFX_ASSERT(p_src_apb != p_dst_apb); in apb_connection_create()
151 NRFX_ASSERT(p_src_apb); in apb_connection_create()
[all …]
Dnrfx_gppi_dppi_ppib_lumos.c189 NRFX_ASSERT(src_dppi_channel == dst_dppi_channel); in create_ppib_connection()
282 NRFX_ASSERT(false); in nrfx_gppi_event_endpoint_setup()
290 NRFX_ASSERT(false); in nrfx_gppi_task_endpoint_setup()
298 NRFX_ASSERT(false); in nrfx_gppi_event_endpoint_clear()
306 NRFX_ASSERT(false); in nrfx_gppi_task_endpoint_clear()
322 NRFX_ASSERT(false); in nrfx_gppi_fork_endpoint_setup()
338 NRFX_ASSERT(false); in nrfx_gppi_fork_endpoint_clear()
347 NRFX_ASSERT(src_domain); in nrfx_gppi_channel_endpoints_setup()
348 NRFX_ASSERT(dst_domain); in nrfx_gppi_channel_endpoints_setup()
364 NRFX_ASSERT(false); in nrfx_gppi_channel_endpoints_setup()
[all …]
/hal_nordic-3.6.0/nrfx/drivers/src/
Dnrfx_rramc.c107 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rramc_all_erase()
116 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rramc_byte_write()
117 NRFX_ASSERT(is_valid_address(address, true)); in nrfx_rramc_byte_write()
118 NRFX_ASSERT(fit_in_memory(address, true, 1)); in nrfx_rramc_byte_write()
125 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rramc_bytes_write()
126 NRFX_ASSERT(src); in nrfx_rramc_bytes_write()
127 NRFX_ASSERT(is_valid_address(address, true)); in nrfx_rramc_bytes_write()
128 NRFX_ASSERT(fit_in_memory(address, true, num_bytes)); in nrfx_rramc_bytes_write()
135 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rramc_word_write()
136 NRFX_ASSERT(is_valid_address(address, true)); in nrfx_rramc_word_write()
[all …]
Dnrfx_ipc.c55 NRFX_ASSERT(handler); in nrfx_ipc_init()
74 NRFX_ASSERT(p_config); in nrfx_ipc_config_load()
75 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_config_load()
95 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_uninit()
122 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_enable()
130 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_disable()
138 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_group_enable()
146 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_group_disable()
154 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_channel_assign()
155 NRFX_ASSERT(channel_index < IPC_CH_NUM); in nrfx_ipc_receive_event_channel_assign()
[all …]
Dnrfx_nvmc.c185 NRFX_ASSERT(bytes_count <= (NVMC_BYTES_IN_WORD - byte_shift)); in partial_word_create()
263 NRFX_ASSERT(is_valid_address(addr, false)); in nrfx_nvmc_page_erase()
305 NRFX_ASSERT(is_valid_address(addr, false)); in nrfx_nvmc_page_partial_erase_init()
321 NRFX_ASSERT(m_partial_erase_page_addr != NVMC_PARTIAL_ERASE_INVALID_ADDR); in nrfx_nvmc_page_partial_erase_continue()
351 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_byte_writable_check()
359 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_halfword_writable_check()
360 NRFX_ASSERT(is_halfword_aligned(addr)); in nrfx_nvmc_halfword_writable_check()
377 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_word_writable_check()
378 NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); in nrfx_nvmc_word_writable_check()
386 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_byte_write()
[all …]
Dnrfx_timer.c124 NRFX_ASSERT(p_config); in nrfx_timer_init()
148 NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); in nrfx_timer_init()
167 NRFX_ASSERT(p_config); in nrfx_timer_reconfigure()
168 NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); in nrfx_timer_reconfigure()
188 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_uninit()
210 NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_timer_enable()
219 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_disable()
228 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_is_enabled()
235 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_resume()
243 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_pause()
[all …]
Dnrfx_grtc.c205 NRFX_ASSERT(p_chan_data); in cc_channel_prepare()
218 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_grtc_active_request_set()
229 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_grtc_syscounter_get()
230 NRFX_ASSERT(p_counter); in nrfx_grtc_syscounter_get()
269 NRFX_ASSERT(p_channel); in nrfx_grtc_channel_alloc()
285 NRFX_ASSERT(channel < NRF_GRTC_SYSCOUNTER_CC_COUNT); in nrfx_grtc_channel_free()
360 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_grtc_rtcounter_cc_disable()
395 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_grtc_rtcomparesync_int_enable()
406 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_grtc_rtcomparesync_int_disable()
417 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_grtc_rtcounter_cc_absolute_set()
[all …]
Dnrfx_adc.c61 NRFX_ASSERT(p_config); in nrfx_adc_init()
93 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_adc_uninit()
116 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_channel_enable()
128 NRFX_ASSERT(p_channel != p_curr_channel); in nrfx_adc_channel_enable()
139 NRFX_ASSERT(m_cb.p_head); in nrfx_adc_channel_disable()
140 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_channel_disable()
148 NRFX_ASSERT(p_curr_channel != NULL); in nrfx_adc_channel_disable()
164 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_all_channels_disable()
171 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_adc_sample()
172 NRFX_ASSERT(!nrf_adc_busy_check(NRF_ADC)); in nrfx_adc_sample()
[all …]
Dnrfx_power.c112 NRFX_ASSERT(p_config); in nrfx_power_init()
145 NRFX_ASSERT(m_initialized); in nrfx_power_uninit()
173 NRFX_ASSERT(p_config != NULL); in nrfx_power_pof_init()
233 NRFX_ASSERT(p_config != NULL); in nrfx_power_sleepevt_init()
273 NRFX_ASSERT(p_config != NULL); in nrfx_power_usbevt_init()
317 NRFX_ASSERT(m_pofwarn_handler != NULL); in nrfx_power_irq_handler()
326 NRFX_ASSERT(m_sleepevt_handler != NULL); in nrfx_power_irq_handler()
333 NRFX_ASSERT(m_sleepevt_handler != NULL); in nrfx_power_irq_handler()
342 NRFX_ASSERT(m_usbevt_handler != NULL); in nrfx_power_irq_handler()
349 NRFX_ASSERT(m_usbevt_handler != NULL); in nrfx_power_irq_handler()
[all …]
Dnrfx_rtc.c72 NRFX_ASSERT(p_config); in nrfx_rtc_init()
73 NRFX_ASSERT(handler); in nrfx_rtc_init()
110 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_rtc_uninit()
130 NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rtc_enable()
139 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_rtc_disable()
148 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_rtc_cc_disable()
149 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_rtc_cc_disable()
182 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_rtc_cc_set()
183 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_rtc_cc_set()
228 NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rtc_tick_enable()
[all …]
Dnrfx_qspi.c125 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in qspi_xfer()
126 NRFX_ASSERT(p_buffer != NULL); in qspi_xfer()
416 NRFX_ASSERT(p_config); in nrfx_qspi_init()
457 NRFX_ASSERT(p_config); in nrfx_qspi_reconfigure()
485 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_timeout_signal()
494 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_cinstr_xfer()
539 NRFX_ASSERT(p_config->wipwait); in nrfx_qspi_cinstr_xfer()
557 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_cinstr_quick_send()
558 NRFX_ASSERT(p_tx_buffer); in nrfx_qspi_cinstr_quick_send()
566 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_lfm_start()
[all …]
Dnrfx_rng.c55 NRFX_ASSERT(p_config); in nrfx_rng_init()
56 NRFX_ASSERT(handler); in nrfx_rng_init()
79 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_start()
87 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_stop()
94 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_uninit()
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/simple_blocking/
Dmain.c142 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
146 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
166 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
173 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
176 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
187 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
194 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
211 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
218 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
221 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
[all …]
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/simple_non_blocking/
Dmain.c155 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
184 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
188 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
208 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
215 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
218 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
231 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
246 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
253 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
256 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
[all …]
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/advanced_blocking/
Dmain.c109 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
113 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
120 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
129 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
132 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
142 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
151 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
162 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/maximum_performance/
Dmain.c160 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
176 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
243 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
252 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
271 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
286 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
289 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
297 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
309 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
317 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
[all …]
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/advanced_non_blocking_internal_timer/
Dmain.c144 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
158 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
205 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
208 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
219 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
222 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
226 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
235 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_twim_twis/tx_rx_blocking/
Dmain.c118 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
124 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
135 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
138 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
145 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
148 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_gppi/fork/
Dmain.c119 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
124 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
127 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
151 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
166 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
177 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
194 NRFX_ASSERT(status == NRFX_SUCCESS); in main()

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