Lines Matching refs:NRFX_ASSERT
874 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk)); in nrf_spu_dppi_config_set()
889 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk)); in nrf_spu_gpio_config_set()
905 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk)); in nrf_spu_flashnsc_set()
906 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk)); in nrf_spu_flashnsc_set()
920 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk)); in nrf_spu_ramnsc_set()
921 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk)); in nrf_spu_ramnsc_set()
935 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk)); in nrf_spu_flashregion_set()
948 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk)); in nrf_spu_ramregion_set()
961 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk); in nrf_spu_peripheral_set()
962 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk)); in nrf_spu_peripheral_set()
975 NRFX_ASSERT(!(p_reg->EXTDOMAIN[domain_id].PERM & SPU_EXTDOMAIN_PERM_LOCK_Msk)); in nrf_spu_extdomain_set()
997 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_present_get()
1005 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerprog_get()
1013 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_get()
1022 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_get()
1031 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_get()
1039 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_get()
1047 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_enable()
1057 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_enable()
1068 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_set()
1079 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_set()
1090 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_securemapping_get()
1100 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dma_get()
1109 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_get()
1119 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_set()
1135 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1141 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1148 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1154 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_get()
1160 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1161 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1167 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1168 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1174 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_get()
1175 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_secattr_get()
1181 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_get()
1192 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1200 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_get()
1206 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_get()
1212 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_get()
1218 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1227 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_get()
1235 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1241 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1247 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1254 NRFX_ASSERT(0); in nrf_spu_feature_secattr_get()
1268 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1274 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1281 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1287 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_get()
1293 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1294 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1300 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1301 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1307 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_get()
1308 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_lock_get()
1314 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_get()
1325 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1333 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_get()
1339 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_get()
1345 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_get()
1351 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1360 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_get()
1368 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1374 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1380 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1387 NRFX_ASSERT(0); in nrf_spu_feature_lock_get()
1402 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1408 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1415 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1421 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_get()
1427 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1428 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1434 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1435 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1441 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_get()
1442 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_block_get()
1448 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_get()
1459 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1467 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_get()
1473 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_get()
1479 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_get()
1485 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1494 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_get()
1502 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1508 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1514 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1521 NRFX_ASSERT(0); in nrf_spu_feature_block_get()
1536 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1542 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1549 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1555 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_get()
1561 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1562 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1568 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1569 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1575 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_get()
1576 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_ownerid_get()
1582 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_get()
1593 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1601 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_get()
1607 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_get()
1613 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_get()
1619 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1628 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_get()
1636 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1642 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1648 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1655 NRFX_ASSERT(0); in nrf_spu_feature_ownerid_get()
1670 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1681 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1693 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1704 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_set()
1715 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1716 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1727 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1728 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1739 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_set()
1740 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_secattr_set()
1751 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_set()
1772 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1785 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_set()
1796 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_set()
1807 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_set()
1818 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1832 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_set()
1845 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1856 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1867 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1879 NRFX_ASSERT(0); in nrf_spu_feature_secattr_set()
1893 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1902 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1912 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1921 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_enable()
1930 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1931 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1940 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1941 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1950 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_enable()
1951 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_lock_enable()
1960 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_enable()
1977 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1988 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_enable()
1997 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_enable()
2006 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_enable()
2015 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
2027 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_enable()
2038 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2047 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2056 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2066 NRFX_ASSERT(0); in nrf_spu_feature_lock_enable()
2081 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2090 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2100 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2109 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_enable()
2118 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2119 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2128 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2129 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2138 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_enable()
2139 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_block_enable()
2148 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_enable()
2165 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2176 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_enable()
2185 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_enable()
2194 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_enable()
2203 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2215 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_enable()
2226 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2235 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2244 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2254 NRFX_ASSERT(0); in nrf_spu_feature_block_enable()
2270 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2280 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2291 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2301 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_set()
2311 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2312 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2322 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2323 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2333 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_set()
2334 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_ownerid_set()
2344 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_set()
2363 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2375 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_set()
2385 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_set()
2395 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_set()
2405 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2418 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_set()
2430 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2440 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2450 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2461 NRFX_ASSERT(0); in nrf_spu_feature_ownerid_set()