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Searched refs:NRFX_ASSERT (Results 1 – 25 of 88) sorted by relevance

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/hal_nordic-3.5.0/nrfx/hal/
Dnrf_spu.h828 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk)); in nrf_spu_dppi_config_set()
843 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk)); in nrf_spu_gpio_config_set()
859 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk)); in nrf_spu_flashnsc_set()
860 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk)); in nrf_spu_flashnsc_set()
874 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk)); in nrf_spu_ramnsc_set()
875 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk)); in nrf_spu_ramnsc_set()
889 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk)); in nrf_spu_flashregion_set()
902 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk)); in nrf_spu_ramregion_set()
915 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk); in nrf_spu_peripheral_set()
916 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk)); in nrf_spu_peripheral_set()
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Dnrf_egu.h305 NRFX_ASSERT(p_reg); in nrf_egu_task_trigger()
312 NRFX_ASSERT(p_reg); in nrf_egu_task_address_get()
323 NRFX_ASSERT(p_reg); in nrf_egu_event_check()
329 NRFX_ASSERT(p_reg); in nrf_egu_event_clear()
337 NRFX_ASSERT(p_reg); in nrf_egu_event_address_get()
348 NRFX_ASSERT(p_reg); in nrf_egu_int_enable()
354 NRFX_ASSERT(p_reg); in nrf_egu_int_enable_check()
360 NRFX_ASSERT(p_reg); in nrf_egu_int_disable()
374 NRFX_ASSERT(p_reg); in nrf_egu_subscribe_set()
382 NRFX_ASSERT(p_reg); in nrf_egu_subscribe_clear()
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Dnrf_acl.h119 NRFX_ASSERT(region_id < ACL_REGIONS_COUNT); in nrf_acl_region_set()
120 NRFX_ASSERT(address % nrf_ficr_codepagesize_get(NRF_FICR) == 0); in nrf_acl_region_set()
121 NRFX_ASSERT(size <= NRF_ACL_REGION_SIZE_MAX); in nrf_acl_region_set()
122 NRFX_ASSERT(size != 0); in nrf_acl_region_set()
123 NRFX_ASSERT(size % nrf_ficr_codepagesize_get(NRF_FICR) == 0); in nrf_acl_region_set()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_saadc/simple_blocking/
Dmain.c127 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
144 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
151 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
154 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
165 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
172 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
188 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
195 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
198 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
212 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
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/hal_nordic-3.5.0/nrfx/drivers/src/
Dnrfx_nvmc.c185 NRFX_ASSERT(bytes_count <= (NVMC_BYTES_IN_WORD - byte_shift)); in partial_word_create()
263 NRFX_ASSERT(is_valid_address(addr, false)); in nrfx_nvmc_page_erase()
305 NRFX_ASSERT(is_valid_address(addr, false)); in nrfx_nvmc_page_partial_erase_init()
321 NRFX_ASSERT(m_partial_erase_page_addr != NVMC_PARTIAL_ERASE_INVALID_ADDR); in nrfx_nvmc_page_partial_erase_continue()
351 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_byte_writable_check()
359 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_halfword_writable_check()
360 NRFX_ASSERT(is_halfword_aligned(addr)); in nrfx_nvmc_halfword_writable_check()
377 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_word_writable_check()
378 NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); in nrfx_nvmc_word_writable_check()
386 NRFX_ASSERT(is_valid_address(addr, true)); in nrfx_nvmc_byte_write()
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Dnrfx_ipc.c52 NRFX_ASSERT(handler); in nrfx_ipc_init()
70 NRFX_ASSERT(p_config); in nrfx_ipc_config_load()
71 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_config_load()
89 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_uninit()
108 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_enable()
114 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_disable()
120 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_group_enable()
126 NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); in nrfx_ipc_receive_event_group_disable()
132 NRFX_ASSERT(channel_index < IPC_CH_NUM); in nrfx_ipc_receive_event_channel_assign()
140 NRFX_ASSERT(channel_index < IPC_CH_NUM); in nrfx_ipc_send_task_channel_assign()
Dnrfx_egu.c109 NRFX_ASSERT(p_instance); in nrfx_egu_init()
132 NRFX_ASSERT(p_instance); in nrfx_egu_int_enable()
133 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_egu_int_enable()
134 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].handler); in nrfx_egu_int_enable()
142 NRFX_ASSERT(p_instance); in nrfx_egu_int_disable()
143 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_egu_int_disable()
150 NRFX_ASSERT(p_instance); in nrfx_egu_trigger()
151 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_egu_trigger()
152 NRFX_ASSERT(event_idx < nrf_egu_channel_count(p_instance->p_reg)); in nrfx_egu_trigger()
159 NRFX_ASSERT(p_instance); in nrfx_egu_uninit()
Dnrfx_power.c112 NRFX_ASSERT(p_config); in nrfx_power_init()
145 NRFX_ASSERT(m_initialized); in nrfx_power_uninit()
168 NRFX_ASSERT(p_config != NULL); in nrfx_power_pof_init()
217 NRFX_ASSERT(p_config != NULL); in nrfx_power_sleepevt_init()
257 NRFX_ASSERT(p_config != NULL); in nrfx_power_usbevt_init()
301 NRFX_ASSERT(m_pofwarn_handler != NULL); in nrfx_power_irq_handler()
310 NRFX_ASSERT(m_sleepevt_handler != NULL); in nrfx_power_irq_handler()
317 NRFX_ASSERT(m_sleepevt_handler != NULL); in nrfx_power_irq_handler()
326 NRFX_ASSERT(m_usbevt_handler != NULL); in nrfx_power_irq_handler()
333 NRFX_ASSERT(m_usbevt_handler != NULL); in nrfx_power_irq_handler()
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Dnrfx_qdec.c115 NRFX_ASSERT(p_instance); in nrfx_qdec_init()
116 NRFX_ASSERT(p_config); in nrfx_qdec_init()
117 NRFX_ASSERT(handler); in nrfx_qdec_init()
151 NRFX_ASSERT(p_config); in nrfx_qdec_reconfigure()
169 NRFX_ASSERT(p_instance); in nrfx_qdec_uninit()
173 NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_qdec_uninit()
198 NRFX_ASSERT(p_instance); in nrfx_qdec_enable()
202 NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); in nrfx_qdec_enable()
212 NRFX_ASSERT(p_instance); in nrfx_qdec_disable()
216 NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_POWERED_ON); in nrfx_qdec_disable()
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Dnrfx_adc.c61 NRFX_ASSERT(p_config); in nrfx_adc_init()
104 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_channel_enable()
116 NRFX_ASSERT(p_channel != p_curr_channel); in nrfx_adc_channel_enable()
127 NRFX_ASSERT(m_cb.p_head); in nrfx_adc_channel_disable()
128 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_channel_disable()
136 NRFX_ASSERT(p_curr_channel != NULL); in nrfx_adc_channel_disable()
152 NRFX_ASSERT(!nrfx_adc_is_busy()); in nrfx_adc_all_channels_disable()
159 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_adc_sample()
160 NRFX_ASSERT(!nrf_adc_busy_check(NRF_ADC)); in nrfx_adc_sample()
169 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_adc_sample_convert()
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Dnrfx_timer.c142 NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); in nrfx_timer_init()
161 NRFX_ASSERT(p_config); in nrfx_timer_reconfigure()
162 NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); in nrfx_timer_reconfigure()
194 NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); in nrfx_timer_enable()
202 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_disable()
210 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_is_enabled()
216 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_resume()
223 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_pause()
230 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_clear()
236 NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_timer_increment()
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Dnrfx_wdt.c63 NRFX_ASSERT(ticks <= UINT32_MAX); in wdt_configure()
86 NRFX_ASSERT(p_config); in nrfx_wdt_init()
123 NRFX_ASSERT(p_config); in nrfx_wdt_reconfigure()
141 NRFX_ASSERT(p_cb->alloc_index != 0); in nrfx_wdt_enable()
142 NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); in nrfx_wdt_enable()
151 NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_POWERED_ON); in nrfx_wdt_feed()
163 NRFX_ASSERT(p_channel_id); in nrfx_wdt_channel_alloc()
164 NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); in nrfx_wdt_channel_alloc()
185 NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_POWERED_ON); in nrfx_wdt_channel_feed()
Dnrfx_gpiote.c346 NRFX_ASSERT(err == NRFX_SUCCESS); in release_handler()
608 NRFX_ASSERT(p_channel); in nrfx_gpiote_channel_get()
675 NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_gpiote_uninit()
717 NRFX_ASSERT(nrfy_gpio_pin_present_check(pin)); in nrfx_gpiote_out_set()
718 NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); in nrfx_gpiote_out_set()
726 NRFX_ASSERT(nrfy_gpio_pin_present_check(pin)); in nrfx_gpiote_out_clear()
727 NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); in nrfx_gpiote_out_clear()
735 NRFX_ASSERT(nrfy_gpio_pin_present_check(pin)); in nrfx_gpiote_out_toggle()
736 NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); in nrfx_gpiote_out_toggle()
744 NRFX_ASSERT(nrfy_gpio_pin_present_check(pin)); in nrfx_gpiote_out_task_enable()
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Dnrfx_rng.c55 NRFX_ASSERT(p_config); in nrfx_rng_init()
56 NRFX_ASSERT(handler); in nrfx_rng_init()
79 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_start()
87 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_stop()
94 NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_rng_uninit()
Dnrfx_qspi.c113 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in qspi_xfer()
114 NRFX_ASSERT(p_buffer != NULL); in qspi_xfer()
332 NRFX_ASSERT(p_config); in nrfx_qspi_init()
370 NRFX_ASSERT(p_config); in nrfx_qspi_reconfigure()
398 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_cinstr_xfer()
441 NRFX_ASSERT(p_config->wipwait); in nrfx_qspi_cinstr_xfer()
465 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_lfm_start()
466 NRFX_ASSERT(p_config->length == NRF_QSPI_CINSTR_LEN_1B); in nrfx_qspi_lfm_start()
493 NRFX_ASSERT(!(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))); in nrfx_qspi_lfm_start()
514 NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); in nrfx_qspi_lfm_xfer()
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Dnrfx_comp.c105 NRFX_ASSERT(p_config); in nrfx_comp_init()
106 NRFX_ASSERT(event_handler); in nrfx_comp_init()
157 NRFX_ASSERT(p_config); in nrfx_comp_reconfigure()
174 NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED); in nrfx_comp_uninit()
203 NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); in nrfx_comp_start()
214 NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); in nrfx_comp_stop()
224 NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); in nrfx_comp_sample()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_saadc/advanced_blocking/
Dmain.c93 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
98 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
107 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
110 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
120 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
129 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
139 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_saadc/simple_non_blocking/
Dmain.c144 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
167 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
188 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
195 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
198 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
211 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
226 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
233 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
236 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
251 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_saadc/maximum_performance/
Dmain.c150 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
166 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
226 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
235 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
260 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
275 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
278 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
286 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
298 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
312 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_saadc/advanced_non_blocking_internal_timer/
Dmain.c133 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
147 NRFX_ASSERT(status == NRFX_SUCCESS); in saadc_handler()
187 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
194 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
205 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
208 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
215 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_gppi/fork/
Dmain.c115 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
119 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
122 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
145 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
160 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
171 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
188 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_twim_twis/tx_rx_blocking/
Dmain.c118 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
124 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
135 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
138 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
145 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
148 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_twim_twis/tx_rx_non_blocking/
Dmain.c129 NRFX_ASSERT(status == NRFX_SUCCESS); in twim_handler()
165 NRFX_ASSERT(status == NRFX_SUCCESS); in twis_handler()
171 NRFX_ASSERT(status == NRFX_SUCCESS); in twis_handler()
200 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
206 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
224 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/samples/src/nrfx_spim_spis/advanced_non_blocking/
Dmain.c210 NRFX_ASSERT(status == NRFX_SUCCESS); in spis_handler()
233 NRFX_ASSERT(status == NRFX_SUCCESS); in spis_handler()
262 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
271 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
281 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
287 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
300 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
309 NRFX_ASSERT(status == NRFX_SUCCESS); in main()
/hal_nordic-3.5.0/nrfx/drivers/include/
Dnrfx_ipc.h182 NRFX_ASSERT(mem_index < NRFX_ARRAY_SIZE(NRF_IPC->GPMEM)); in nrfx_ipc_gpmem_set()
188 NRFX_ASSERT(mem_index < NRFX_ARRAY_SIZE(NRF_IPC->GPMEM)); in nrfx_ipc_gpmem_get()
194 NRFX_ASSERT(send_index < IPC_CONF_NUM); in nrfx_ipc_signal()
200 NRFX_ASSERT(event_index < IPC_CONF_NUM); in nrfx_ipc_receive_config_set()
206 NRFX_ASSERT(send_index < IPC_CONF_NUM); in nrfx_ipc_send_config_set()

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