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Searched refs:mode (Results 1 – 25 of 29) sorted by relevance

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/hal_microchip-latest/mec5/drivers/
Dmec_bbled.c111 static void bbled_set_mode(struct mec_bbled_regs *regs, uint8_t mode) in bbled_set_mode() argument
114 (((uint32_t)mode << MEC_BBLED_CONFIG_CTRL_Pos) & MEC_BBLED_CONFIG_CTRL_Msk)); in bbled_set_mode()
245 uint8_t mode = 0; in mec_hal_bbled_breathe_pwm_width() local
251 mode = bbled_get_mode(regs); in mec_hal_bbled_breathe_pwm_width()
252 if ((mode == MEC_BBLED_MODE_BREATHE) || (mode == MEC_BBLED_MODE_BLINK)) { in mec_hal_bbled_breathe_pwm_width()
313 int mec_hal_bbled_mode(struct mec_bbled_regs *regs, uint8_t mode) in mec_hal_bbled_mode() argument
315 if (!regs || (mode > MEC_BBLED_MODE_ON)) { in mec_hal_bbled_mode()
319 bbled_set_mode(regs, mode); in mec_hal_bbled_mode()
332 uint8_t mode = 0; in mec_hal_bbled_breathe_config() local
338 mode = bbled_get_mode(regs); in mec_hal_bbled_breathe_config()
[all …]
Dmec_qspi.c379 uint32_t mode = base->MODE & (uint32_t)~MEC_QSPI_MODE_CS_Msk; in qspi_cs_select() local
381 mode |= (((uint32_t)cs << MEC_QSPI_MODE_CS_Pos) & MEC_QSPI_MODE_CS_Msk); in qspi_cs_select()
382 base->MODE = mode; in qspi_cs_select()
1256 uint32_t descr, ldchan, mode; in mec_hal_qspi_load_descrs() local
1266 mode = 0; in mec_hal_qspi_load_descrs()
1284 mode |= MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos); in mec_hal_qspi_load_descrs()
1294 mode |= MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos); in mec_hal_qspi_load_descrs()
1302 | MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos))) | mode; in mec_hal_qspi_load_descrs()
Dmec_ecs.c76 void mec_hal_ecs_debug_port(enum mec_debug_mode mode) in mec_hal_ecs_debug_port() argument
80 switch (mode) { in mec_hal_ecs_debug_port()
Dmec_i3c.c502 uint8_t mode; in MEC_HAL_I3C_Enable() local
505 mode = DEV_OPERATION_MODE_CTL; in MEC_HAL_I3C_Enable()
508 mode = DEV_OPERATION_MODE_TGT; in MEC_HAL_I3C_Enable()
535 _i3c_operation_mode_set(regs, mode); in MEC_HAL_I3C_Enable()
542 _i3c_enable(regs, mode, enable_dma); in MEC_HAL_I3C_Enable()
Dmec_ecs_api.h65 void mec_hal_ecs_debug_port(enum mec_debug_mode mode);
Dmec_bbled_api.h88 int mec_hal_bbled_mode(struct mec_bbled_regs *regs, uint8_t mode);
Dmec_i3c_pvt.c375 void _i3c_operation_mode_set(struct mec_i3c_host_regs *regs, uint8_t mode) in _i3c_operation_mode_set() argument
377 regs->DEV_EXT_CTRL = mode & 0x1; in _i3c_operation_mode_set()
386 void _i3c_enable(struct mec_i3c_host_regs *regs, uint8_t mode, bool enable_dma) in _i3c_enable() argument
395 if (DEV_OPERATION_MODE_CTL == mode) in _i3c_enable()
Dmec_i3c_pvt.h606 void _i3c_operation_mode_set(struct mec_i3c_host_regs *regs, uint8_t mode);
615 void _i3c_enable(struct mec_i3c_host_regs *regs, uint8_t mode, bool enable_dma);
/hal_microchip-latest/mpfs/drivers/mss/mss_rtc/
Dmss_rtc.c91 uint8_t mode, in MSS_RTC_init() argument
117 if (MSS_RTC_CALENDAR_MODE == mode) in MSS_RTC_init()
386 uint8_t mode; in MSS_RTC_set_calendar_count_alarm() local
388 mode = (uint8_t)(mss_rtc->MODE_REG & MODE_CLK_MODE_MASK); in MSS_RTC_set_calendar_count_alarm()
392 ASSERT(MSS_RTC_CALENDAR_MODE == mode); in MSS_RTC_set_calendar_count_alarm()
394 if (MSS_RTC_CALENDAR_MODE == mode) in MSS_RTC_set_calendar_count_alarm()
426 required_mode_reg = mode | MODE_WAKEUP_EN_MASK | MODE_WAKEUP_CONTINUE_MASK; in MSS_RTC_set_calendar_count_alarm()
474 uint8_t mode; in MSS_RTC_set_binary_count_alarm() local
476 mode = (uint8_t)(mss_rtc->MODE_REG & MODE_CLK_MODE_MASK); in MSS_RTC_set_binary_count_alarm()
480 ASSERT(MSS_RTC_BINARY_MODE == mode); in MSS_RTC_set_binary_count_alarm()
[all …]
Dmss_rtc.h354 uint8_t mode,
/hal_microchip-latest/mpfs/drivers/mss/mss_timer/
Dmss_timer.h204 MSS_TIM1_init(TIMER_TypeDef* timer, mss_timer_mode_t mode) in MSS_TIM1_init() argument
212 timer->TIM1_CTRL = TIM1_MODE_MASK & ((uint32_t)mode << TIM1_MODE_SHIFT); in MSS_TIM1_init()
390 MSS_TIM2_init(TIMER_TypeDef* timer, mss_timer_mode_t mode) in MSS_TIM2_init() argument
396 timer->TIM2_CTRL = TIM2_MODE_MASK & ((uint32_t)mode << TIM2_MODE_SHIFT); in MSS_TIM2_init()
565 MSS_TIM64_init(TIMER_TypeDef* timer, mss_timer_mode_t mode) in MSS_TIM64_init() argument
573 timer->TIM64_CTRL = TIM64_MODE_MASK & ((uint32_t)mode << TIM64_MODE_SHIFT); in MSS_TIM64_init()
/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_mpu.h96 __IO uint64_t mode : 8; member
146 MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode |= (0x1U << 7U); in MSS_MPU_lock_region()
167 MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode |= permission; in MSS_MPU_set_permission()
182 *permission = MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode & 0x7U; in MSS_MPU_get_permission()
Dmss_mpu.c262 MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode = (uint8_t)(permission | in MSS_MPU_configure()
290 reg = MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode; in MSS_MPU_get_config()
/hal_microchip-latest/mpfs/drivers/mss/mss_usb/
Dmss_usb_common_cif.c627 mss_usb_dma_mode_t mode; in MSS_USB_CIF_tx_ep_configure() local
666 mode = MSS_USB_DMA_MODE1; in MSS_USB_CIF_tx_ep_configure()
676 mode = MSS_USB_DMA_MODE0; in MSS_USB_CIF_tx_ep_configure()
681 mode, in MSS_USB_CIF_tx_ep_configure()
702 mss_usb_dma_mode_t mode; in MSS_USB_CIF_rx_ep_configure() local
743 mode = MSS_USB_DMA_MODE1; in MSS_USB_CIF_rx_ep_configure()
753 mode = MSS_USB_DMA_MODE0; in MSS_USB_CIF_rx_ep_configure()
758 mode, in MSS_USB_CIF_rx_ep_configure()
Dmss_usb_common_reg_io.h1332 uint8_t mode; in MSS_USB_CIF_dma_get_burst_mode() local
1333 mode = (USB->DMA_CHANNEL[dma_channel].CNTL & in MSS_USB_CIF_dma_get_burst_mode()
1336 return (mss_usb_dma_burst_mode_t)(mode >> DMA_CNTL_REG_DMA_BURST_MODE_SHIFT); in MSS_USB_CIF_dma_get_burst_mode()
/hal_microchip-latest/mpfs/mpfs_hal/startup_gcc/
Dnewlib_stubs.c193 int _open(const char *name, int flags, int mode);
194 int _open(const char *name, int flags, int mode) in _open() argument
198 (void)mode; in _open()
/hal_microchip-latest/mpfs/drivers/mss/mss_mmuart/
Dmss_uart.c1276 mss_uart_ready_mode_t mode in MSS_UART_set_ready_mode() argument
1279 ASSERT(MSS_UART_INVALID_READY_MODE > mode); in MSS_UART_set_ready_mode()
1281 if (MSS_UART_INVALID_READY_MODE > mode ) in MSS_UART_set_ready_mode()
1284 ((MSS_UART_READY_MODE0 == mode) ? (this_uart->hw_reg->FCR &= ~RDYMODE_MASK) : in MSS_UART_set_ready_mode()
1296 mss_uart_usart_mode_t mode in MSS_UART_set_usart_mode() argument
1299 ASSERT(MSS_UART_INVALID_SYNC_MODE > mode); in MSS_UART_set_usart_mode()
1301 if (MSS_UART_INVALID_SYNC_MODE > mode) in MSS_UART_set_usart_mode()
1307 this_uart->hw_reg->MM0 |= (uint8_t)mode; in MSS_UART_set_usart_mode()
Dmss_uart.h3224 mss_uart_ready_mode_t mode
3264 mss_uart_usart_mode_t mode
/hal_microchip-latest/mpfs/drivers/mss/mss_can/
Dmss_can.c166 mss_can_mode_t mode in MSS_CAN_set_mode() argument
170 if (CANOP_SW_RESET == mode) in MSS_CAN_set_mode()
177 this_can->hw_reg->Command.L = (uint32_t)mode; in MSS_CAN_set_mode()
Dmss_can.h1173 mss_can_mode_t mode
/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dmss_ethernet_mac.h2252 mss_mac_hash_mode_t mode
Dvsc8575_phy.c269 g_phy.mode = VTSS_PHY_MODE_ANEG; in MSS_MAC_VSC8575_phy_init()
454 phy_config.mode = VSC_PHY_MODE_ANEG; in MSS_MAC_VSC8575_phy_init()
/hal_microchip-latest/mpfs/boards/icicle-kit-es/platform_config/linker/
Dmpfs-ddr-e51.ld38 secure boot. When not using secure boot (mode 0,1), this area is still reserved
/hal_microchip-latest/mpfs/platform_config_reference/linker/
Dmpfs-ddr-loaded-by-boot-loader.ld48 secure boot. When not using secure boot (mode 0,1), this area is still reserved
Dmpfs-lim.ld32 secure boot. When not using secure boot (mode 0,1), this area is still reserved

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