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Searched refs:mask (Results 1 – 23 of 23) sorted by relevance

/hal_microchip-latest/mpfs/hal/
Dhw_reg_access.h72 uint32_t mask,
95 uint32_t mask
143 uint_fast16_t mask,
165 uint_fast16_t mask
213 uint_fast8_t mask,
235 uint_fast8_t mask
/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_mpu.c306 uint64_t mask = 0U; in pmp_get_napot_base_and_range() local
309 mask = (mask - 1U) >> 1U; in pmp_get_napot_base_and_range()
311 while (mask) in pmp_get_napot_base_and_range()
313 if ((reg & mask) == mask) in pmp_get_napot_base_and_range()
316 base = reg & ~mask; in pmp_get_napot_base_and_range()
319 mask >>= 1U; in pmp_get_napot_base_and_range()
/hal_microchip-latest/mec5/drivers/
Dmec_gpio.c34 uint8_t mask; member
396 int mec_hal_gpio_set_config_mask(uint32_t pin, uint32_t cfg, uint32_t mask) in mec_hal_gpio_set_config_mask() argument
404 uint16_t pin_cfg = MEC_MMCR16_RD(&MEC_GPIO->CTRL[pin]) & (uint16_t)~mask; in mec_hal_gpio_set_config_mask()
406 pin_cfg |= (uint16_t)(cfg & mask); in mec_hal_gpio_set_config_mask()
418 uint32_t msk0 = mec_cfg_tbl[prop_id].mask; in mec_hal_gpio_get_ctrl_property()
432 uint32_t msk0 = mec_cfg_tbl[prop_id].mask; in mec_hal_gpio_set_ctrl_property()
453 uint32_t msk0 = mec_cfg_tbl[prop_id].mask; in mec_hal_gpio_get_property()
477 uint32_t msk0 = mec_cfg_tbl[prop_id].mask; in mec_hal_gpio_set_property()
521 uint32_t mask = mec_cfg_tbl[prop].mask; in mec_hal_gpio_set_props() local
522 uint32_t val = gprops[n].val & mask; in mec_hal_gpio_set_props()
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Dmec_mailbox.c129 int mec_hal_mbox_sirq_en_mask(struct mec_mbox_regs *base, uint8_t val, uint8_t mask) in mec_hal_mbox_sirq_en_mask() argument
135 if (mask) { in mec_hal_mbox_sirq_en_mask()
136 base->ECSMIM = (base->ECSMIM & ~mask) | (val & mask); in mec_hal_mbox_sirq_en_mask()
Dmec_i3c.c219 uint32_t mask = 0xFFFFFFFFU; in MEC_HAL_I3C_Target_Interrupts_Init() local
225 _i3c_intr_sts_clear(regs, mask); in MEC_HAL_I3C_Target_Interrupts_Init()
228 mask = sbit_RESP_READY_STS | sbit_CCC_UPDATED_STS | \ in MEC_HAL_I3C_Target_Interrupts_Init()
234 _i3c_intr_sts_enable(regs, mask); in MEC_HAL_I3C_Target_Interrupts_Init()
237 _i3c_intr_sgnl_enable(regs, mask); in MEC_HAL_I3C_Target_Interrupts_Init()
252 uint32_t mask = 0xFFFFFFFFU; in MEC_HAL_I3C_Controller_Interrupts_Init() local
259 _i3c_intr_sts_clear(regs, mask); in MEC_HAL_I3C_Controller_Interrupts_Init()
262 mask = sbit_RESP_READY_STS | sbit_TRANSFER_ABORT_STS | \ in MEC_HAL_I3C_Controller_Interrupts_Init()
267 _i3c_intr_sts_enable(regs, mask); in MEC_HAL_I3C_Controller_Interrupts_Init()
270 _i3c_intr_sgnl_enable(regs, mask); in MEC_HAL_I3C_Controller_Interrupts_Init()
Dmec_gpio_api.h339 int mec_hal_gpio_set_config_mask(uint32_t pin, uint32_t new_cfg, uint32_t mask);
344 int mec_hal_gpio_set_ctrl_mask(uint32_t pin, uint32_t val, uint32_t mask);
356 int mec_hal_gpio_ctrl2_mask(const uint32_t pin, uint32_t val, uint32_t mask);
377 int mec_hal_gpio_parout_port_set_bits(const uint8_t port, const uint32_t mask);
380 const uint32_t mask);
388 int mec_hal_gpio_port_ia_status_clr_mask(uint8_t port, uint32_t mask);
Dmec_emi.c250 int mec_hal_emi_swi_host_clear_enable(struct mec_emi_regs *regs, uint16_t mask, uint16_t enable) in mec_hal_emi_swi_host_clear_enable() argument
256 regs->IHCEN = (regs->IHCEN & ~mask) | (enable & mask); in mec_hal_emi_swi_host_clear_enable()
Dmec_mailbox_api.h46 int mec_hal_mbox_sirq_en_mask(struct mec_mbox_regs *base, uint8_t val, uint8_t mask);
Dmec_i3c_pvt.c33 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_clear() argument
35 regs->INTR_STS = mask; in _i3c_intr_sts_clear()
43 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_enable() argument
45 regs->INTR_EN = mask; in _i3c_intr_sts_enable()
125 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sgnl_enable() argument
127 regs->INTR_SIG_EN = mask; in _i3c_intr_sgnl_enable()
Dmec_i2c.c537 int mec_hal_i2c_smb_intr_ctrl(struct mec_i2c_smb_ctx *ctx, uint32_t mask, uint8_t enable) in mec_hal_i2c_smb_intr_ctrl() argument
549 if (mask & MEC_BIT(MEC_I2C_IEN_BYTE_MODE_POS)) { in mec_hal_i2c_smb_intr_ctrl()
558 if (mask & MEC_BIT(MEC_I2C_IEN_IDLE_POS)) { in mec_hal_i2c_smb_intr_ctrl()
561 if (mask & MEC_BIT(MEC_I2C_NL_IEN_CM_DONE_POS)) { in mec_hal_i2c_smb_intr_ctrl()
564 if (mask & MEC_BIT(MEC_I2C_NL_IEN_TM_DONE_POS)) { in mec_hal_i2c_smb_intr_ctrl()
567 if (mask & MEC_BIT(MEC_I2C_NL_IEN_AAT_POS)) { in mec_hal_i2c_smb_intr_ctrl()
Dmec_emi_api.h89 int mec_hal_emi_swi_host_clear_enable(struct mec_emi_regs *regs, uint16_t mask, uint16_t enable);
Dmec_pcr.c253 int mec_hal_pcr_slp_en_mask(uint8_t regid, uint32_t val, uint32_t mask) in mec_hal_pcr_slp_en_mask() argument
259 MEC_PCR->SLP_EN[regid] = (MEC_PCR->SLP_EN[regid] & ~mask) | (val & mask); in mec_hal_pcr_slp_en_mask()
Dmec_espi.c21 uint32_t mask = (MEC_ESPI_IO_CAP0_PC_SUPP_Msk | MEC_ESPI_IO_CAP0_VW_SUPP_Msk in set_supported_channels() local
41 iobase->CAP0 = (uint8_t)((iobase->CAP0 & ~mask) | temp); in set_supported_channels()
46 uint32_t mask = MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk; in set_supported_max_freq() local
52 iobase->CAP1 = (uint8_t)((iobase->CAP1 & ~mask) | temp); in set_supported_max_freq()
Dmec_espi_taf.c326 int mec_hal_espi_taf_pr_dirty_clr_mask(struct mec_espi_taf_regs *regs, uint32_t mask) in mec_hal_espi_taf_pr_dirty_clr_mask() argument
332 regs->PR_DIRTY = mask; in mec_hal_espi_taf_pr_dirty_clr_mask()
Dmec_i3c_pvt.h579 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask);
580 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
581 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask);
Dmec_espi_host_dev.c208 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask) in mec_hal_espi_iobar_mask_set() argument
224 temp |= (((uint32_t)mask << MEC_ESPI_IO_EC_LDN_MSK_MSK_Pos) | MEC_ESPI_IO_EC_LDN_MSK_MSK_Msk); in mec_hal_espi_iobar_mask_set()
Dmec_espi_taf.h236 int mec_hal_espi_taf_pr_dirty_clr_mask(struct mec_espi_taf_regs *regs, uint32_t mask);
Dmec_pcr_api.h170 int mec_hal_pcr_slp_en_mask(uint8_t regid, uint32_t val, uint32_t mask);
Dmec_espi_pc.h164 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask);
Dmec_i2c_api.h174 int mec_hal_i2c_smb_intr_ctrl(struct mec_i2c_smb_ctx *ctx, uint32_t mask, uint8_t en);
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c125 static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC_PATTERN pattern, M…
2178 uint8_t mask; in ddr_setup() local
2181 mask = 0x3U; in ddr_setup()
2185 mask = 0xFU; in ddr_setup()
2187 … error = MTC_test(mask, start_address, size, MTC_COUNTING_PATTERN, MTC_ADD_SEQUENTIAL, &error); in ddr_setup()
2190 … error |= MTC_test(mask, start_address, size, MTC_COUNTING_PATTERN, MTC_ADD_SEQUENTIAL, &error); in ddr_setup()
2191 … error |= MTC_test(mask, start_address, size, MTC_WALKING_ONE, MTC_ADD_SEQUENTIAL, &error); in ddr_setup()
2192 … error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM, MTC_ADD_SEQUENTIAL, &error); in ddr_setup()
2193 …error |= MTC_test(mask, start_address, size, MTC_NO_REPEATING_PSEUDO_RANDOM, MTC_ADD_SEQUENTIAL, &… in ddr_setup()
2194 … error |= MTC_test(mask, start_address, size, MTC_ALT_ONES_ZEROS, MTC_ADD_SEQUENTIAL, &error); in ddr_setup()
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/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dmss_ethernet_mac.c4369 temp_reg |= (uint32_t)comparer->mask; in MSS_MAC_set_type_2_compare()
4429 comparer->mask = (uint16_t)p_reg[comparer_no]; in MSS_MAC_get_type_2_compare()
4725 uint32_t mask; in MSS_MAC_set_tx_cutthru() local
4730 … mask = (0U != this_mac->is_emac) ? GEM_DMA_EMAC_CUTTHRU_THRESHOLD : GEM_DMA_TX_CUTTHRU_THRESHOLD; in MSS_MAC_set_tx_cutthru()
4738 *p_reg = GEM_DMA_CUTTHRU | (level & mask); in MSS_MAC_set_tx_cutthru()
4751 uint32_t mask; in MSS_MAC_set_rx_cutthru() local
4756 … mask = (0U != this_mac->is_emac) ? GEM_DMA_EMAC_CUTTHRU_THRESHOLD : GEM_DMA_RX_CUTTHRU_THRESHOLD; in MSS_MAC_set_rx_cutthru()
4764 *p_reg = GEM_DMA_CUTTHRU | (level & mask); in MSS_MAC_set_rx_cutthru()
4778 uint32_t mask; in MSS_MAC_get_tx_cutthru() local
4783 … mask = (0U != this_mac->is_emac) ? GEM_DMA_EMAC_CUTTHRU_THRESHOLD : GEM_DMA_TX_CUTTHRU_THRESHOLD; in MSS_MAC_get_tx_cutthru()
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Dmss_ethernet_mac_types.h1145 uint16_t mask; /*!< 16 bit mask if data is 16 bit */ member