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Searched refs:iobase (Results 1 – 11 of 11) sorted by relevance

/hal_microchip-latest/mec5/drivers/
Dmec_espi.c19 static void set_supported_channels(struct mec_espi_io_regs *iobase, uint32_t capabilities) in set_supported_channels() argument
41 iobase->CAP0 = (uint8_t)((iobase->CAP0 & ~mask) | temp); in set_supported_channels()
44 static void set_supported_max_freq(struct mec_espi_io_regs *iobase, uint32_t capabilities) in set_supported_max_freq() argument
52 iobase->CAP1 = (uint8_t)((iobase->CAP1 & ~mask) | temp); in set_supported_max_freq()
58 static uint32_t get_max_freq(struct mec_espi_io_regs *iobase) in get_max_freq() argument
61 ((iobase->CAP1 & MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk) >> MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Pos); in get_max_freq()
66 static void set_supported_io_modes(struct mec_espi_io_regs *iobase, uint32_t capabilities) in set_supported_io_modes() argument
68 uint32_t temp = iobase->CAP1 & ~(MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Msk); in set_supported_io_modes()
74 iobase->CAP1 = (uint8_t)(temp & 0xffu); in set_supported_io_modes()
80 static uint32_t get_supported_io_modes(struct mec_espi_io_regs *iobase) in get_supported_io_modes() argument
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Dmec_espi_fc.c61 uint32_t mec_hal_espi_fc_en_status(struct mec_espi_io_regs *iobase) in mec_hal_espi_fc_en_status() argument
63 return (iobase->FCSTS & 0x3u); in mec_hal_espi_fc_en_status()
66 void mec_hal_espi_fc_ready_set(struct mec_espi_io_regs *iobase) in mec_hal_espi_fc_ready_set() argument
68 iobase->FCRDY = MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos); in mec_hal_espi_fc_ready_set()
71 int mec_hal_espi_fc_is_ready(struct mec_espi_io_regs *iobase) in mec_hal_espi_fc_is_ready() argument
73 if (iobase->FCRDY & MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos)) { in mec_hal_espi_fc_is_ready()
80 int mec_hal_espi_fc_is_busy(struct mec_espi_io_regs *iobase) in mec_hal_espi_fc_is_busy() argument
82 if (iobase->FCCFG & MEC_BIT(MEC_ESPI_IO_FCCFG_BUSY_Pos)) { in mec_hal_espi_fc_is_busy()
96 void mec_hal_espi_fc_op_start(struct mec_espi_io_regs *iobase, uint32_t flags) in mec_hal_espi_fc_op_start() argument
98 iobase->FCSTS = MEC_ESPI_FC_ERR_ALL | MEC_BIT(MEC_ESPI_IO_FCSTS_DONE_Pos); in mec_hal_espi_fc_op_start()
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Dmec_espi_oob.c100 void mec_hal_espi_oob_ready_set(struct mec_espi_io_regs *iobase) in mec_hal_espi_oob_ready_set() argument
102 iobase->OOBRDY = MEC_BIT(MEC_ESPI_IO_OOBRDY_OOB_READY_Pos); in mec_hal_espi_oob_ready_set()
105 int mec_hal_espi_oob_is_ready(struct mec_espi_io_regs *iobase) in mec_hal_espi_oob_is_ready() argument
107 if (iobase->OOBRDY & MEC_BIT(MEC_ESPI_IO_OOBRDY_OOB_READY_Pos)) { in mec_hal_espi_oob_is_ready()
118 uint32_t mec_hal_espi_oob_en_status(struct mec_espi_io_regs *iobase) in mec_hal_espi_oob_en_status() argument
120 uint32_t txsts = iobase->OOBTXSTS; in mec_hal_espi_oob_en_status()
135 uint32_t mec_hal_espi_oob_max_pkt_size(struct mec_espi_io_regs *iobase) in mec_hal_espi_oob_max_pkt_size() argument
139 sz = (iobase->OOBRXC & MEC_ESPI_IO_OOBRXC_MAX_PLD_SZ_Msk) >> MEC_ESPI_IO_OOBRXC_MAX_PLD_SZ_Pos; in mec_hal_espi_oob_max_pkt_size()
159 int mec_hal_espi_oob_buffer_set(struct mec_espi_io_regs *iobase, uint8_t dir, in mec_hal_espi_oob_buffer_set() argument
164 if (!iobase || !buf) { in mec_hal_espi_oob_buffer_set()
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Dmec_espi_pc.c41 void mec_hal_espi_pc_ready_set(struct mec_espi_io_regs *iobase) in mec_hal_espi_pc_ready_set() argument
43 iobase->PCRDY = MEC_BIT(MEC_ESPI_IO_PCRDY_PC_READY_Pos); in mec_hal_espi_pc_ready_set()
46 int mec_hal_espi_pc_is_ready(struct mec_espi_io_regs *iobase) in mec_hal_espi_pc_is_ready() argument
48 if (iobase->PCRDY & MEC_BIT(MEC_ESPI_IO_PCRDY_PC_READY_Pos)) { in mec_hal_espi_pc_is_ready()
58 uint32_t mec_hal_espi_pc_en_status(struct mec_espi_io_regs *iobase) in mec_hal_espi_pc_en_status() argument
60 uint32_t temp = iobase->PCSTS & (MEC_ESPI_IO_PCSTS_PCEN_VAL_Msk in mec_hal_espi_pc_en_status()
70 uint32_t mec_hal_espi_pc_bm_status(struct mec_espi_io_regs *iobase) in mec_hal_espi_pc_bm_status() argument
72 uint32_t temp = iobase->PCSTS & (MEC_ESPI_IO_PCSTS_PCBM_VAL_Msk in mec_hal_espi_pc_bm_status()
78 uint32_t mec_hal_espi_pc_status(struct mec_espi_io_regs *iobase) in mec_hal_espi_pc_status() argument
81 uint32_t temp = iobase->PCSTS; in mec_hal_espi_pc_status()
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Dmec_espi_oob.h61 void mec_hal_espi_oob_ready_set(struct mec_espi_io_regs *iobase);
62 int mec_hal_espi_oob_is_ready(struct mec_espi_io_regs *iobase);
67 uint32_t mec_hal_espi_oob_en_status(struct mec_espi_io_regs *iobase);
69 uint32_t mec_hal_espi_oob_max_pkt_size(struct mec_espi_io_regs *iobase);
71 int mec_hal_espi_oob_buffer_set(struct mec_espi_io_regs *iobase, uint8_t dir,
73 void mec_hal_espi_oob_rx_buffer_avail(struct mec_espi_io_regs *iobase);
75 void mec_hal_espi_oob_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en);
77 void mec_hal_espi_oob_tx_start(struct mec_espi_io_regs *iobase, uint8_t tag, uint8_t start);
80 uint8_t mec_hal_espi_oob_rx_tag(struct mec_espi_io_regs *iobase);
82 uint32_t mec_hal_espi_oob_received_len(struct mec_espi_io_regs *iobase);
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Dmec_espi_fc.h57 void mec_hal_espi_fc_ready_set(struct mec_espi_io_regs *iobase);
58 int mec_hal_espi_fc_is_ready(struct mec_espi_io_regs *iobase);
61 uint32_t mec_hal_espi_fc_en_status(struct mec_espi_io_regs *iobase);
68 uint32_t mec_hal_espi_fc_max_read_req_sz(struct mec_espi_io_regs *iobase);
69 uint32_t mec_hal_espi_fc_max_pld_sz(struct mec_espi_io_regs *iobase);
71 int mec_hal_espi_fc_is_busy(struct mec_espi_io_regs *iobase);
72 void mec_hal_espi_fc_op_start(struct mec_espi_io_regs *iobase, uint32_t flags);
73 void mec_hal_espi_fc_op_abort(struct mec_espi_io_regs *iobase);
74 void mec_hal_espi_fc_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en);
75 uint32_t mec_hal_espi_fc_status(struct mec_espi_io_regs *iobase);
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Dmec_espi_pc.h106 void mec_hal_espi_pc_ready_set(struct mec_espi_io_regs *iobase);
108 int mec_hal_espi_pc_is_ready(struct mec_espi_io_regs *iobase);
113 uint32_t mec_hal_espi_pc_en_status(struct mec_espi_io_regs *iobase);
114 uint32_t mec_hal_espi_pc_bm_status(struct mec_espi_io_regs *iobase);
117 uint32_t mec_hal_espi_pc_status(struct mec_espi_io_regs *iobase);
118 void mec_hal_espi_pc_status_clr(struct mec_espi_io_regs *iobase, uint32_t bitmap);
119 void mec_hal_espi_pc_status_clr_all(struct mec_espi_io_regs *iobase);
121 void mec_hal_espi_pc_intr_en(struct mec_espi_io_regs *iobase, uint32_t bitmap);
122 void mec_hal_espi_pc_intr_dis(struct mec_espi_io_regs *iobase, uint32_t bitmap);
125 uint64_t mec_hal_espi_pc_error_addr(struct mec_espi_io_regs *iobase);
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Dmec_espi_core.h253 struct mec_espi_io_regs *iobase; member
269 int mec_hal_espi_capability_set(struct mec_espi_io_regs *iobase,
272 int mec_hal_espi_capability_get(struct mec_espi_io_regs *iobase,
275 int mec_hal_espi_cap_set(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id, uint32_t cfg);
276 uint32_t mec_hal_espi_cap_get(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id);
278 void mec_hal_espi_reset_change_clr(struct mec_espi_io_regs *iobase);
279 void mec_hal_espi_reset_change_intr_en(struct mec_espi_io_regs *iobase, uint8_t enable);
286 uint32_t mec_hal_espi_reset_state(struct mec_espi_io_regs *iobase);
291 void mec_hal_espi_activate(struct mec_espi_io_regs *iobase, uint8_t enable);
292 int mec_hal_espi_is_activated(struct mec_espi_io_regs *iobase);
Dmec_espi_host_dev.c92 static uint8_t mec_espi_sirq_get(struct mec_espi_io_regs *iobase, uint8_t sirq_idx) in mec_espi_sirq_get() argument
98 return iobase->SERIRQ[sirq_idx]; in mec_espi_sirq_get()
102 static void espi_sirq_set(struct mec_espi_io_regs *iobase, uint8_t sirq_idx, uint8_t slot) in espi_sirq_set() argument
108 iobase->SERIRQ[sirq_idx] = slot; in espi_sirq_set()
431 uint8_t mec_hal_espi_ld_sirq_num(struct mec_espi_io_regs *iobase, uint8_t ldn) in mec_hal_espi_ld_sirq_num() argument
435 if (!iobase || !ldi) { in mec_hal_espi_ld_sirq_num()
445 uint8_t mec_hal_espi_ld_sirq_get(struct mec_espi_io_regs *iobase, uint8_t ldn, uint8_t ldn_sirq_id) in mec_hal_espi_ld_sirq_get() argument
450 if (!iobase || !ldi) { in mec_hal_espi_ld_sirq_get()
460 return mec_espi_sirq_get(iobase, idx); in mec_hal_espi_ld_sirq_get()
463 void mec_hal_espi_ld_sirq_set(struct mec_espi_io_regs *iobase, uint8_t ldn, in mec_hal_espi_ld_sirq_set() argument
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Dmec_espi_vw.h209 int mec_hal_espi_vw_is_enabled(struct mec_espi_io_regs * const iobase);
210 uint32_t mec_hal_espi_vw_en_status(struct mec_espi_io_regs * const iobase);
215 void mec_hal_espi_vw_ready_set(struct mec_espi_io_regs * const iobase);
216 int mec_hal_espi_vw_is_ready(struct mec_espi_io_regs * const iobase);
Dmec_espi_vw.c61 int mec_hal_espi_vw_is_enabled(struct mec_espi_io_regs *const iobase) in mec_hal_espi_vw_is_enabled() argument
63 if (iobase->VWSTS & MEC_BIT(MEC_ESPI_IO_VWSTS_CHEN_Pos)) { in mec_hal_espi_vw_is_enabled()
75 uint32_t mec_hal_espi_vw_en_status(struct mec_espi_io_regs *const iobase) in mec_hal_espi_vw_en_status() argument
77 uint32_t ensts = iobase->VWSTS & MEC_BIT(MEC_ESPI_IO_VWSTS_CHEN_Pos); in mec_hal_espi_vw_en_status()
106 void mec_hal_espi_vw_ready_set(struct mec_espi_io_regs * const iobase) in mec_hal_espi_vw_ready_set() argument
108 iobase->VWRDY = MEC_BIT(MEC_ESPI_IO_VWRDY_VW_READY_Pos); in mec_hal_espi_vw_ready_set()
111 int mec_hal_espi_vw_is_ready(struct mec_espi_io_regs * const iobase) in mec_hal_espi_vw_is_ready() argument
113 if (iobase->VWRDY & MEC_BIT(MEC_ESPI_IO_VWRDY_VW_READY_Pos)) { in mec_hal_espi_vw_is_ready()