19 static void set_supported_channels(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_supported_channels()  argument
41     iobase->CAP0 = (uint8_t)((iobase->CAP0 & ~mask) | temp);  in set_supported_channels()
44 static void set_supported_max_freq(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_supported_max_freq()  argument
52     iobase->CAP1 = (uint8_t)((iobase->CAP1 & ~mask) | temp);  in set_supported_max_freq()
58 static uint32_t get_max_freq(struct mec_espi_io_regs *iobase)  in get_max_freq()  argument
61         ((iobase->CAP1 & MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk) >> MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Pos);  in get_max_freq()
66 static void set_supported_io_modes(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_supported_io_modes()  argument
68     uint32_t temp = iobase->CAP1 & ~(MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Msk);  in set_supported_io_modes()
74     iobase->CAP1 = (uint8_t)(temp & 0xffu);  in set_supported_io_modes()
80 static uint32_t get_supported_io_modes(struct mec_espi_io_regs *iobase)  in get_supported_io_modes()  argument
83         ((iobase->CAP1 & MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Msk) >> MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Pos);  in get_supported_io_modes()
88 static void set_supported_alert_io_pin_mode(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_supported_alert_io_pin_mode()  argument
90     uint32_t temp = iobase->CAP1 & ~(MEC_ESPI_IO_CAP1_ALERT_OD_SUPP_Msk);  in set_supported_alert_io_pin_mode()
96     iobase->CAP1 = (uint8_t)(temp & 0xffu);  in set_supported_alert_io_pin_mode()
99 static void set_pc_capabilities(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_pc_capabilities()  argument
101     uint32_t temp = iobase->CAPPC & ~(MEC_ESPI_IO_CAPPC_PC_MAX_PLD_Msk);  in set_pc_capabilities()
107     iobase->CAPPC = (uint8_t)(temp & 0xffu);  in set_pc_capabilities()
110 static uint32_t get_pc_max_pld_size(struct mec_espi_io_regs *iobase)  in get_pc_max_pld_size()  argument
113         ((iobase->CAPPC & MEC_ESPI_IO_CAPPC_PC_MAX_PLD_Msk) >> MEC_ESPI_IO_CAPPC_PC_MAX_PLD_Pos);  in get_pc_max_pld_size()
118 static void set_vw_capabilities(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_vw_capabilities()  argument
120     uint32_t temp = iobase->CAPVW & ~(MEC_ESPI_IO_CAPVW_MAX_VW_CNT_Msk);  in set_vw_capabilities()
126     iobase->CAPVW = (uint8_t)(temp & 0xffu);  in set_vw_capabilities()
129 static uint32_t get_vw_groups_max_cnt(struct mec_espi_io_regs *iobase)  in get_vw_groups_max_cnt()  argument
132         ((iobase->CAPVW & MEC_ESPI_IO_CAPVW_MAX_VW_CNT_Msk) >> MEC_ESPI_IO_CAPVW_MAX_VW_CNT_Pos);  in get_vw_groups_max_cnt()
137 static void set_oob_capabilities(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_oob_capabilities()  argument
139     uint32_t temp = iobase->CAPOOB & ~(MEC_ESPI_IO_CAPOOB_MAX_PLD_SIZE_Msk);  in set_oob_capabilities()
145     iobase->CAPOOB = (uint8_t)(temp & 0xffu);  in set_oob_capabilities()
148 static uint32_t get_oob_pld_size(struct mec_espi_io_regs *iobase)  in get_oob_pld_size()  argument
151 …   ((iobase->CAPOOB & MEC_ESPI_IO_CAPOOB_MAX_PLD_SIZE_Msk) >> MEC_ESPI_IO_CAPOOB_MAX_PLD_SIZE_Pos);  in get_oob_pld_size()
156 static void set_fc_max_pld(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_fc_max_pld()  argument
164     iobase->CAPFC = (iobase->CAPFC & ~msk) | regval;  in set_fc_max_pld()
167 static uint32_t get_fc_pld_size(struct mec_espi_io_regs *iobase)  in get_fc_pld_size()  argument
170 …      ((iobase->CAPFC & MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Msk) >> MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Pos);  in get_fc_pld_size()
209 static void set_fc_shared_mode(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_fc_shared_mode()  argument
214     iobase->CAPFC = (iobase->CAPFC & ~msk) | regval;  in set_fc_shared_mode()
217 static uint32_t get_fc_shared_mode(struct mec_espi_io_regs *iobase)  in get_fc_shared_mode()  argument
219     uint32_t fcsh = fc_sharing_get(iobase->CAPFC);  in get_fc_shared_mode()
224 static void set_fc_capabilities(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_fc_capabilities()  argument
244     iobase->CAPFC = (iobase->CAPFC & ~msk) | regval;  in set_fc_capabilities()
247 static uint32_t get_fc_taf_max_rdsz(struct mec_espi_io_regs *iobase)  in get_fc_taf_max_rdsz()  argument
250     uint32_t capfc = iobase->CAPFC;  in get_fc_taf_max_rdsz()
263 static void set_pltrst_source(struct mec_espi_io_regs *iobase, uint32_t capabilities)  in set_pltrst_source()  argument
268         iobase->PLTRST_SRC |= MEC_BIT(MEC_ESPI_IO_PLTRST_SRC_SEL_Pos);  in set_pltrst_source()
270         iobase->PLTRST_SRC &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_PLTRST_SRC_SEL_Pos);  in set_pltrst_source()
278 void mec_hal_espi_reset_change_clr(struct mec_espi_io_regs *iobase)  in mec_hal_espi_reset_change_clr()  argument
280     iobase->ERIS = MEC_BIT(MEC_ESPI_IO_ERIS_CHG_Pos);  in mec_hal_espi_reset_change_clr()
285 uint32_t mec_hal_espi_reset_state(struct mec_espi_io_regs *iobase)  in mec_hal_espi_reset_state()  argument
287     return iobase->ERIS & (MEC_ESPI_IO_ERIS_CHG_Msk | MEC_ESPI_IO_ERIS_STATE_Msk);  in mec_hal_espi_reset_state()
290 void mec_hal_espi_reset_change_intr_en(struct mec_espi_io_regs *iobase, uint8_t enable)  in mec_hal_espi_reset_change_intr_en()  argument
293         iobase->ERIE |= MEC_BIT(MEC_ESPI_IO_ERIE_CHG_INTR_Pos);  in mec_hal_espi_reset_change_intr_en()
295         iobase->ERIE &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_ERIE_CHG_INTR_Pos);  in mec_hal_espi_reset_change_intr_en()
330     struct mec_espi_io_regs *iobase = cfg->iobase;  in mec_hal_espi_init()  local
333     set_supported_channels(iobase, cfg->capabilities);  in mec_hal_espi_init()
334     set_supported_max_freq(iobase, cfg->capabilities);  in mec_hal_espi_init()
335     set_supported_io_modes(iobase, cfg->capabilities);  in mec_hal_espi_init()
336     set_supported_alert_io_pin_mode(iobase, cfg->capabilities);  in mec_hal_espi_init()
337     set_pc_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
338     set_vw_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
339     set_oob_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
340     set_fc_capabilities(iobase, cfg->capabilities);  in mec_hal_espi_init()
341     set_pltrst_source(iobase, cfg->capabilities);  in mec_hal_espi_init()
343     mec_hal_espi_reset_change_intr_en(iobase, 0);  in mec_hal_espi_init()
344     mec_hal_espi_reset_change_clr(iobase);  in mec_hal_espi_init()
395 void mec_hal_espi_activate(struct mec_espi_io_regs *iobase, uint8_t enable)  in mec_hal_espi_activate()  argument
398         iobase->ACTV |= MEC_BIT(MEC_ESPI_IO_ACTV_EN_Pos);  in mec_hal_espi_activate()
400         iobase->ACTV &= (uint32_t)~MEC_BIT(MEC_ESPI_IO_ACTV_EN_Pos);  in mec_hal_espi_activate()
404 int mec_hal_espi_is_activated(struct mec_espi_io_regs *iobase)  in mec_hal_espi_is_activated()  argument
406     if (iobase) {  in mec_hal_espi_is_activated()
407         if (iobase->ACTV & MEC_BIT(MEC_ESPI_IO_ACTV_EN_Pos)) {  in mec_hal_espi_is_activated()
415 int mec_hal_espi_capability_set(struct mec_espi_io_regs *iobase,  in mec_hal_espi_capability_set()  argument
418     if (!iobase) {  in mec_hal_espi_capability_set()
424         set_supported_max_freq(iobase, cfg);  in mec_hal_espi_capability_set()
427         set_supported_io_modes(iobase, cfg);  in mec_hal_espi_capability_set()
430         set_supported_alert_io_pin_mode(iobase, cfg);  in mec_hal_espi_capability_set()
434             iobase->CAP0 |= MEC_BIT(MEC_ESPI_IO_CAP0_PC_SUPP_Pos);  in mec_hal_espi_capability_set()
436             iobase->CAP0 &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_CAP0_PC_SUPP_Pos);  in mec_hal_espi_capability_set()
440         set_pc_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
444             iobase->CAP0 |= MEC_BIT(MEC_ESPI_IO_CAP0_VW_SUPP_Pos);  in mec_hal_espi_capability_set()
446             iobase->CAP0 &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_CAP0_VW_SUPP_Pos);  in mec_hal_espi_capability_set()
450         set_vw_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
454             iobase->CAP0 |= MEC_BIT(MEC_ESPI_IO_CAP0_OOB_SUPP_Pos);  in mec_hal_espi_capability_set()
456             iobase->CAP0 &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_CAP0_OOB_SUPP_Pos);  in mec_hal_espi_capability_set()
460         set_oob_capabilities(iobase, cfg);  in mec_hal_espi_capability_set()
464             iobase->CAP0 |= MEC_BIT(MEC_ESPI_IO_CAP0_FC_SUPP_Pos);  in mec_hal_espi_capability_set()
466             iobase->CAP0 &= (uint8_t)~MEC_BIT(MEC_ESPI_IO_CAP0_FC_SUPP_Pos);  in mec_hal_espi_capability_set()
470         set_fc_max_pld(iobase, cfg);  in mec_hal_espi_capability_set()
473         set_fc_shared_mode(iobase, cfg);  in mec_hal_espi_capability_set()
482 int mec_hal_espi_capabilities_get(struct mec_espi_io_regs *iobase, uint32_t *cfg)  in mec_hal_espi_capabilities_get()  argument
486     if (!iobase || !cfg) {  in mec_hal_espi_capabilities_get()
491     cv |= ((get_max_freq(iobase) << MEC_ESPI_CFG_MAX_SUPP_FREQ_POS)  in mec_hal_espi_capabilities_get()
495     cv |= get_supported_io_modes(iobase);  in mec_hal_espi_capabilities_get()
498     if (iobase->CAP1 & MEC_BIT(MEC_ESPI_IO_CAP1_ALERT_OD_SUPP_Pos)) {  in mec_hal_espi_capabilities_get()
503     if (iobase->CAP0 & MEC_BIT(MEC_ESPI_IO_CAP0_PC_SUPP_Pos)) {  in mec_hal_espi_capabilities_get()
506     cv |= get_pc_max_pld_size(iobase);  in mec_hal_espi_capabilities_get()
509     if (iobase->CAP0 & MEC_BIT(MEC_ESPI_IO_CAP0_VW_SUPP_Pos)) {  in mec_hal_espi_capabilities_get()
512     cv |= get_vw_groups_max_cnt(iobase);  in mec_hal_espi_capabilities_get()
515     if (iobase->CAP0 & MEC_BIT(MEC_ESPI_IO_CAP0_OOB_SUPP_Pos)) {  in mec_hal_espi_capabilities_get()
518     cv |= get_oob_pld_size(iobase);  in mec_hal_espi_capabilities_get()
521     if (iobase->CAP0 & MEC_BIT(MEC_ESPI_IO_CAP0_FC_SUPP_Pos)) {  in mec_hal_espi_capabilities_get()
524     cv |= get_fc_pld_size(iobase);  in mec_hal_espi_capabilities_get()
525     cv |= get_fc_shared_mode(iobase);  in mec_hal_espi_capabilities_get()
526     cv |= get_fc_taf_max_rdsz(iobase);  in mec_hal_espi_capabilities_get()
533 static void set_espi_global_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_global_cap()  argument
551     iobase->CAP0 = (iobase->CAP0 & (uint8_t)~msk) | (uint8_t)(cap & msk);  in set_espi_global_cap()
563     iobase->CAP1 = (iobase->CAP1 & (uint8_t)~msk) | (uint8_t)(cap & msk);  in set_espi_global_cap()
571     iobase->PLTRST_SRC = (iobase->PLTRST_SRC & (uint8_t)~msk) | (uint8_t)(cap & msk);  in set_espi_global_cap()
574 static uint32_t get_espi_global_cap(struct mec_espi_io_regs *iobase)  in get_espi_global_cap()  argument
577     uint32_t hwval = iobase->CAP0;  in get_espi_global_cap()
592     hwval = iobase->CAP1;  in get_espi_global_cap()
601     if (iobase->PLTRST_SRC & MEC_BIT(MEC_ESPI_IO_PLTRST_SRC_SEL_Pos)) {  in get_espi_global_cap()
608 static void set_espi_pc_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_pc_cap()  argument
614     iobase->CAPPC = (uint8_t)((iobase->CAPPC & (uint8_t)~msk) | (cap & msk));  in set_espi_pc_cap()
617 static uint32_t get_espi_pc_cap(struct mec_espi_io_regs *iobase)  in get_espi_pc_cap()  argument
620         ((iobase->CAPPC & MEC_ESPI_IO_CAPPC_PC_MAX_PLD_Msk) >> MEC_ESPI_IO_CAPPC_PC_MAX_PLD_Pos);  in get_espi_pc_cap()
625 static void set_espi_vw_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_vw_cap()  argument
632     iobase->CAPVW = (uint8_t)((iobase->CAPVW & (uint8_t)~msk) | (cap & msk));  in set_espi_vw_cap()
635 static uint32_t get_espi_vw_cap(struct mec_espi_io_regs *iobase)  in get_espi_vw_cap()  argument
638         ((iobase->CAPVW & MEC_ESPI_IO_CAPVW_MAX_VW_CNT_Msk) >> MEC_ESPI_IO_CAPVW_MAX_VW_CNT_Pos);  in get_espi_vw_cap()
643 static void set_espi_oob_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_oob_cap()  argument
650     iobase->CAPOOB = (uint8_t)((iobase->CAPOOB & (uint8_t)~msk) | (cap | msk));  in set_espi_oob_cap()
653 static uint32_t get_espi_oob_cap(struct mec_espi_io_regs *iobase)  in get_espi_oob_cap()  argument
656 …   ((iobase->CAPOOB & MEC_ESPI_IO_CAPOOB_MAX_PLD_SIZE_Msk) >> MEC_ESPI_IO_CAPOOB_MAX_PLD_SIZE_Pos);  in get_espi_oob_cap()
661 static void set_espi_fc_cap(struct mec_espi_io_regs *iobase, uint32_t cfg)  in set_espi_fc_cap()  argument
667     iobase->TAFEBS =  in set_espi_fc_cap()
677     iobase->CAPFC = (uint8_t)((iobase->CAPFC & (uint8_t)~msk) | (cap & msk));  in set_espi_fc_cap()
680 static uint32_t get_espi_fc_cap(struct mec_espi_io_regs *iobase)  in get_espi_fc_cap()  argument
682     uint32_t capfc = iobase->CAPFC;  in get_espi_fc_cap()
692     cfg |= (((uint32_t)iobase->TAFEBS & 0xffu) << MEC_ESPI_CAP_FC_TAF_ERBSZ_POS);  in get_espi_fc_cap()
697 int mec_hal_espi_cap_set(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id, uint32_t cfg)  in mec_hal_espi_cap_set()  argument
699     if (!iobase) {  in mec_hal_espi_cap_set()
705         set_espi_global_cap(iobase, cfg);  in mec_hal_espi_cap_set()
708         set_espi_pc_cap(iobase, cfg);  in mec_hal_espi_cap_set()
711         set_espi_vw_cap(iobase, cfg);  in mec_hal_espi_cap_set()
714         set_espi_oob_cap(iobase, cfg);  in mec_hal_espi_cap_set()
717         set_espi_fc_cap(iobase, cfg);  in mec_hal_espi_cap_set()
726 uint32_t mec_hal_espi_cap_get(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id)  in mec_hal_espi_cap_get()  argument
732         cap = get_espi_global_cap(iobase);  in mec_hal_espi_cap_get()
735         cap = get_espi_pc_cap(iobase);  in mec_hal_espi_cap_get()
738         cap = get_espi_vw_cap(iobase);  in mec_hal_espi_cap_get()
741         cap = get_espi_oob_cap(iobase);  in mec_hal_espi_cap_get()
744         cap = get_espi_fc_cap(iobase);  in mec_hal_espi_cap_get()