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Searched refs:ctx (Results 1 – 8 of 8) sorted by relevance

/hal_microchip-latest/mec5/drivers/
Dmec_i2c.c139 int mec_hal_i2c_smb_reset(struct mec_i2c_smb_ctx *ctx) in mec_hal_i2c_smb_reset() argument
141 if (!ctx) { in mec_hal_i2c_smb_reset()
145 const struct mec_i2c_info *info = get_i2c_smb_info(ctx->base); in mec_hal_i2c_smb_reset()
165 static void i2c_config(struct mec_i2c_smb_ctx *ctx, struct mec_i2c_smb_cfg *config, in i2c_config() argument
168 struct mec_i2c_smb_regs *base = ctx->base; in i2c_config()
177 ctx->i2c_ctrl_cached = control; in i2c_config()
197 ctx->i2c_ctrl_cached = control; in i2c_config()
210 int mec_hal_i2c_smb_bus_freq_get(struct mec_i2c_smb_ctx *ctx, uint32_t *bus_freq_hz) in mec_hal_i2c_smb_bus_freq_get() argument
212 if (!ctx || !ctx->base || !bus_freq_hz) { in mec_hal_i2c_smb_bus_freq_get()
216 struct mec_i2c_smb_regs *regs = ctx->base; in mec_hal_i2c_smb_bus_freq_get()
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Dmec_i3c.c56 void MEC_HAL_I3C_Controller_Clk_I2C_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz) in MEC_HAL_I3C_Controller_Clk_I2C_Init() argument
58 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_I2C_Init()
61 const struct mec_i3c_info *info = get_i3c_info(ctx->base); in MEC_HAL_I3C_Controller_Clk_I2C_Init()
65 ctx->devi = info->devi; in MEC_HAL_I3C_Controller_Clk_I2C_Init()
87 void MEC_HAL_I3C_Controller_Clk_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz, in MEC_HAL_I3C_Controller_Clk_Init() argument
90 const struct mec_i3c_info *info = get_i3c_info(ctx->base); in MEC_HAL_I3C_Controller_Clk_Init()
94 ctx->devi = info->devi; in MEC_HAL_I3C_Controller_Clk_Init()
99 MEC_HAL_I3C_Controller_Clk_Cfg(ctx, core_clk_rate_mhz, i3c_freq); in MEC_HAL_I3C_Controller_Clk_Init()
110 void MEC_HAL_I3C_Controller_Clk_Cfg(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz, in MEC_HAL_I3C_Controller_Clk_Cfg() argument
113 struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base; in MEC_HAL_I3C_Controller_Clk_Cfg()
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Dmec_htimer.c25 int mec_hal_htimer_init(struct mec_htmr_regs *regs, struct mec_htimer_context *ctx, in mec_hal_htimer_init() argument
31 if (!ctx) { in mec_hal_htimer_init()
37 ctx->regs = regs; in mec_hal_htimer_init()
38 ctx->devi = MEC_HTMR0_ECIA_INFO; in mec_hal_htimer_init()
42 ctx->regs = regs; in mec_hal_htimer_init()
43 ctx->devi = MEC_HTMR1_ECIA_INFO; in mec_hal_htimer_init()
55 mec_hal_girq_ctrl(ctx->devi, 0); in mec_hal_htimer_init()
65 mec_hal_girq_clr_src(ctx->devi); in mec_hal_htimer_init()
66 mec_hal_girq_ctrl(ctx->devi, irq_en); in mec_hal_htimer_init()
71 ctx->count = ctx->preload; in mec_hal_htimer_init()
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Dmec_i3c_api.h225 void MEC_HAL_I3C_Soft_Reset(struct mec_i3c_ctx *ctx);
227 void MEC_HAL_I3C_Controller_Clk_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
230 void MEC_HAL_I3C_Controller_Clk_Cfg(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
233 void MEC_HAL_I3C_Controller_Clk_I2C_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz);
235 void MEC_HAL_I3C_Target_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
238 void MEC_HAL_I3C_Controller_Interrupts_Init(struct mec_i3c_ctx *ctx);
240 void MEC_HAL_I3C_Thresholds_Init(struct mec_i3c_ctx *ctx);
242 void MEC_HAL_I3C_Thresholds_Response_buf_set(struct mec_i3c_ctx *ctx, uint8_t threshold);
244 void MEC_HAL_I3C_Host_Config(struct mec_i3c_ctx *ctx);
246 void MEC_HAL_I3C_Sec_Host_Config(struct mec_i3c_ctx *ctx);
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Dmec_i2c_api.h136 int mec_hal_i2c_smb_reset(struct mec_i2c_smb_ctx *ctx);
138 int mec_hal_i2c_smb_init(struct mec_i2c_smb_ctx *ctx, struct mec_i2c_smb_cfg *config,
141 int mec_hal_i2c_smb_bus_freq_get(struct mec_i2c_smb_ctx *ctx, uint32_t *bus_freq_hz);
143 int mec_hal_i2c_smb_ctrl_set(struct mec_i2c_smb_ctx *ctx, uint8_t ctrl);
144 uint8_t mec_hal_i2c_smb_ctrl_get(struct mec_i2c_smb_ctx *ctx);
146 int mec_hal_i2c_cmd_ack_ctrl(struct mec_i2c_smb_ctx *ctx, uint8_t ack_en);
148 int mec_hal_i2c_smb_is_bus_owned(struct mec_i2c_smb_ctx *ctx);
150 int mec_hal_i2c_smb_get_target_addr(struct mec_i2c_smb_ctx *ctx, uint8_t target_id,
152 int mec_hal_i2c_smb_set_target_addr(struct mec_i2c_smb_ctx *ctx, uint8_t target_id,
154 int mec_hal_i2c_smb_clr_target_addr(struct mec_i2c_smb_ctx *ctx, uint16_t target_addr);
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Dmec_htimer_api.h45 int mec_hal_htimer_init(struct mec_htmr_regs *regs, struct mec_htimer_context *ctx,
48 void mec_hal_htimer_intr_ctrl(struct mec_htimer_context *ctx, uint8_t enable);
50 uint32_t mec_hal_htimer_status(struct mec_htimer_context *ctx);
51 void mec_hal_htimer_status_clear(struct mec_htimer_context *ctx);
55 void mec_hal_htimer_halt(struct mec_htimer_context *ctx);
56 void mec_hal_htimer_unhalt(struct mec_htimer_context *ctx);
58 void mec_hal_htimer_restart(struct mec_htimer_context *ctx, uint16_t new_count);
Dmec_qspi.c1042 void mec_hal_qspi_context_init(struct mec_qspi_context *ctx) in mec_hal_qspi_context_init() argument
1044 ctx->ndescrs = 0; in mec_hal_qspi_context_init()
1045 ctx->ntxdma = 0; in mec_hal_qspi_context_init()
1046 ctx->nrxdma = 0; in mec_hal_qspi_context_init()
1047 ctx->xflags = 0; in mec_hal_qspi_context_init()
1049 ctx->descrs[n] = 0; in mec_hal_qspi_context_init()
1053 uint8_t mec_hal_qspi_ctx_alloc_ldma_chan(struct mec_qspi_context *ctx, uint8_t is_tx) in mec_hal_qspi_ctx_alloc_ldma_chan() argument
1055 if (!ctx) { in mec_hal_qspi_ctx_alloc_ldma_chan()
1060 if (ctx->ntxdma < MEC5_QSPI_LDMA_CHANNELS) { in mec_hal_qspi_ctx_alloc_ldma_chan()
1061 return ++ctx->ntxdma; in mec_hal_qspi_ctx_alloc_ldma_chan()
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Dmec_qspi_api.h269 void mec_hal_qspi_context_init(struct mec_qspi_context *ctx);
271 uint8_t mec_hal_qspi_ctx_alloc_ldma_chan(struct mec_qspi_context *ctx, uint8_t is_tx);
296 uint32_t mec_hal_qspi_descrs_cfg1(struct mec_qspi_context *ctx, uint32_t nbytes, uint32_t flags);
308 int mec_hal_qspi_cfg_gen_ts_clocks(struct mec_qspi_context *ctx, uint32_t nclocks,
317 int mec_hal_qspi_load_descrs(struct mec_qspi_regs *regs, struct mec_qspi_context *ctx,