56 void MEC_HAL_I3C_Controller_Clk_I2C_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz)  in MEC_HAL_I3C_Controller_Clk_I2C_Init()  argument
58     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
61     const struct mec_i3c_info *info = get_i3c_info(ctx->base);  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
65         ctx->devi = info->devi;  in MEC_HAL_I3C_Controller_Clk_I2C_Init()
87 void MEC_HAL_I3C_Controller_Clk_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,  in MEC_HAL_I3C_Controller_Clk_Init()  argument
90     const struct mec_i3c_info *info = get_i3c_info(ctx->base);  in MEC_HAL_I3C_Controller_Clk_Init()
94         ctx->devi = info->devi;  in MEC_HAL_I3C_Controller_Clk_Init()
99         MEC_HAL_I3C_Controller_Clk_Cfg(ctx, core_clk_rate_mhz, i3c_freq);  in MEC_HAL_I3C_Controller_Clk_Init()
110 void MEC_HAL_I3C_Controller_Clk_Cfg(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,  in MEC_HAL_I3C_Controller_Clk_Cfg()  argument
113     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Clk_Cfg()
135 void MEC_HAL_I3C_Target_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,  in MEC_HAL_I3C_Target_Init()  argument
138     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_Init()
141     const struct mec_i3c_info *info = get_i3c_info(ctx->base);  in MEC_HAL_I3C_Target_Init()
145         ctx->devi = info->devi;  in MEC_HAL_I3C_Target_Init()
184 void MEC_HAL_I3C_Target_MRL_MWL_update(struct mec_i3c_ctx *ctx, uint16_t *max_rd_len,  in MEC_HAL_I3C_Target_MRL_MWL_update()  argument
187     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_MRL_MWL_update()
203 void MEC_HAL_I3C_Target_MRL_MWL_set(struct mec_i3c_ctx *ctx, uint16_t max_rd_len,  in MEC_HAL_I3C_Target_MRL_MWL_set()  argument
206     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Target_MRL_MWL_set()
216 void MEC_HAL_I3C_Target_Interrupts_Init(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Target_Interrupts_Init()  argument
218     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Target_Interrupts_Init()
220     const struct mec_i3c_info *info = get_i3c_info(ctx->base);  in MEC_HAL_I3C_Target_Interrupts_Init()
249 void MEC_HAL_I3C_Controller_Interrupts_Init(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Controller_Interrupts_Init()  argument
251     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Controller_Interrupts_Init()
253     const struct mec_i3c_info *info = get_i3c_info(ctx->base);  in MEC_HAL_I3C_Controller_Interrupts_Init()
282 void MEC_HAL_I3C_Thresholds_Init(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Thresholds_Init()  argument
284     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Thresholds_Init()
326 void MEC_HAL_I3C_Thresholds_Response_buf_set(struct mec_i3c_ctx *ctx, uint8_t threshold)  in MEC_HAL_I3C_Thresholds_Response_buf_set()  argument
328     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Thresholds_Response_buf_set()
338 void MEC_HAL_I3C_Host_Config(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Host_Config()  argument
340     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Host_Config()
360 void MEC_HAL_I3C_Sec_Host_Config(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Sec_Host_Config()  argument
362     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_Sec_Host_Config()
382 void MEC_HAL_I3C_Soft_Reset(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Soft_Reset()  argument
384     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Soft_Reset()
396 void MEC_HAL_I3C_DAT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth)  in MEC_HAL_I3C_DAT_info_get()  argument
398     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_info_get()
410 void MEC_HAL_I3C_DCT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth)  in MEC_HAL_I3C_DCT_info_get()  argument
412     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DCT_info_get()
423 bool MEC_HAL_I3C_Is_Current_Role_Primary(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Is_Current_Role_Primary()  argument
425     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_Primary()
440 bool MEC_HAL_I3C_Is_Current_Role_Master(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Is_Current_Role_Master()  argument
442     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_Master()
458 bool MEC_HAL_I3C_Is_Current_Role_BusMaster(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Is_Current_Role_BusMaster()  argument
460     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Is_Current_Role_BusMaster()
474 void MEC_HAL_I3C_queue_depths_get(struct mec_i3c_ctx *ctx,  in MEC_HAL_I3C_queue_depths_get()  argument
482     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_queue_depths_get()
499 void MEC_HAL_I3C_Enable(struct mec_i3c_ctx *ctx, uint8_t address, uint8_t config)  in MEC_HAL_I3C_Enable()  argument
501     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Enable()
564 void MEC_HAL_I3C_DCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t DCT_idx,  in MEC_HAL_I3C_DCT_read()  argument
567     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DCT_read()
579 void MEC_HAL_I3C_TGT_DEFTGTS_DAT_write(struct mec_i3c_ctx *ctx, uint16_t DCT_start,  in MEC_HAL_I3C_TGT_DEFTGTS_DAT_write()  argument
582     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_DEFTGTS_DAT_write()
589         MEC_HAL_I3C_SDCT_read(ctx, DCT_start, i, &sdct_info);  in MEC_HAL_I3C_TGT_DEFTGTS_DAT_write()
610 void MEC_HAL_I3C_SDCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t idx,  in MEC_HAL_I3C_SDCT_read()  argument
613     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_SDCT_read()
626 void MEC_HAL_I3C_DAT_DynamicAddr_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start,  in MEC_HAL_I3C_DAT_DynamicAddr_write()  argument
629     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_DynamicAddr_write()
645 void MEC_HAL_I3C_DAT_DynamicAddrAssign_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start,  in MEC_HAL_I3C_DAT_DynamicAddrAssign_write()  argument
648     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DAT_DynamicAddrAssign_write()
669 void MEC_HAL_I3C_DO_DAA(struct mec_i3c_ctx *ctx, uint8_t tgt_idx, uint8_t tgts_count,  in MEC_HAL_I3C_DO_DAA()  argument
672     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_DAA()
701 void MEC_HAL_I3C_DO_CCC(struct mec_i3c_ctx *ctx, struct mec_i3c_DO_CCC *tgt, uint8_t *tid_xfer)  in MEC_HAL_I3C_DO_CCC()  argument
703     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_CCC()
769 void MEC_HAL_I3C_DO_Xfer_Prep(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *cmd,  in MEC_HAL_I3C_DO_Xfer_Prep()  argument
772     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_Xfer_Prep()
828 void MEC_HAL_I3C_DO_Xfer(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *tgt)  in MEC_HAL_I3C_DO_Xfer()  argument
830     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_Xfer()
839 void MEC_HAL_I3C_DO_TGT_Xfer(struct mec_i3c_ctx *ctx, uint8_t *data_buf, uint16_t data_len)  in MEC_HAL_I3C_DO_TGT_Xfer()  argument
841     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_DO_TGT_Xfer()
865 void MEC_HAL_I3C_IBI_SIR_Enable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info,  in MEC_HAL_I3C_IBI_SIR_Enable()  argument
868     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_IBI_SIR_Enable()
906 void MEC_HAL_I3C_IBI_SIR_Disable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info,  in MEC_HAL_I3C_IBI_SIR_Disable()  argument
909     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_IBI_SIR_Disable()
934 void MEC_HAL_I3C_TGT_PID_set(struct mec_i3c_ctx *ctx, uint64_t pid, bool pid_random)  in MEC_HAL_I3C_TGT_PID_set()  argument
936     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_PID_set()
948 bool MEC_HAL_I3C_TGT_is_dyn_addr_valid(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_TGT_is_dyn_addr_valid()  argument
950     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_is_dyn_addr_valid()
960 uint8_t MEC_HAL_I3C_TGT_dyn_addr_get(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_TGT_dyn_addr_get()  argument
962     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_dyn_addr_get()
975 void MEC_HAL_I3C_TGT_MXDS_set(struct mec_i3c_ctx *ctx,  in MEC_HAL_I3C_TGT_MXDS_set()  argument
981     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_MXDS_set()
992 int MEC_HAL_I3C_TGT_IBI_SIR_Raise(struct mec_i3c_ctx *ctx,  in MEC_HAL_I3C_TGT_IBI_SIR_Raise()  argument
995     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_SIR_Raise()
1017 int MEC_HAL_I3C_TGT_IBI_MR_Raise(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_TGT_IBI_MR_Raise()  argument
1019     struct mec_i3c_sec_regs *regs = (struct mec_i3c_sec_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_MR_Raise()
1040 void MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle()  argument
1042     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle()
1055 void MEC_HAL_I3C_TGT_Error_Recovery(struct mec_i3c_ctx *ctx, uint8_t err_sts)  in MEC_HAL_I3C_TGT_Error_Recovery()  argument
1057     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_Error_Recovery()
1081 void MEC_HAL_I3C_TGT_RoleSwitch_Resume(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()  argument
1083     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_TGT_RoleSwitch_Resume()
1104 void MEC_HAL_I3C_Xfer_Error_Resume(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Xfer_Error_Resume()  argument
1106     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Xfer_Error_Resume()
1120 void MEC_HAL_I3C_Xfer_Reset(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_Xfer_Reset()  argument
1122     struct mec_i3c_host_regs *regs = (struct mec_i3c_host_regs *)ctx->base;  in MEC_HAL_I3C_Xfer_Reset()
1132 void MEC_HAL_I3C_GIRQ_Status_Clr(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_GIRQ_Status_Clr()  argument
1134     if (ctx) {  in MEC_HAL_I3C_GIRQ_Status_Clr()
1136         mec_hal_girq_clr_src(ctx->devi);  in MEC_HAL_I3C_GIRQ_Status_Clr()
1141 void MEC_HAL_I3C_GIRQ_CTRL(struct mec_i3c_ctx *ctx, int flags)  in MEC_HAL_I3C_GIRQ_CTRL()  argument
1143     if (ctx) {  in MEC_HAL_I3C_GIRQ_CTRL()
1147             mec_hal_girq_ctrl(ctx->devi, 0);  in MEC_HAL_I3C_GIRQ_CTRL()
1151             mec_hal_girq_clr_src(ctx->devi);  in MEC_HAL_I3C_GIRQ_CTRL()
1155             mec_hal_girq_ctrl(ctx->devi, 1);  in MEC_HAL_I3C_GIRQ_CTRL()
1161 int MEC_HAL_I3C_GIRQ_Status(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_GIRQ_Status()  argument
1163     if (!ctx) {  in MEC_HAL_I3C_GIRQ_Status()
1167     return (int)mec_hal_girq_src(ctx->devi);  in MEC_HAL_I3C_GIRQ_Status()
1170 int MEC_HAL_I3C_GIRQ_Result(struct mec_i3c_ctx *ctx)  in MEC_HAL_I3C_GIRQ_Result()  argument
1172     if (!ctx) {  in MEC_HAL_I3C_GIRQ_Result()
1176     return (int)mec_hal_girq_result(ctx->devi);  in MEC_HAL_I3C_GIRQ_Result()