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Searched refs:config (Results 1 – 25 of 29) sorted by relevance

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/hal_microchip-latest/mpfs/drivers/mss/mss_watchdog/
Dmss_watchdog.c36 const mss_watchdog_config_t * config in MSS_WD_configure() argument
45 if (config->timeout_val <= MSS_WDOG_TRIGGER_MAX) in MSS_WD_configure()
47 wdog_hw_base[wd_num]->TRIGGER = config->timeout_val; in MSS_WD_configure()
54 if (config->time_val <= MSS_WDOG_TIMER_MAX) in MSS_WD_configure()
56 wdog_hw_base[wd_num]->MSVP = config->mvrp_val; in MSS_WD_configure()
63 if (config->time_val <= MSS_WDOG_TIMER_MAX) in MSS_WD_configure()
65 wdog_hw_base[wd_num]->TIME = config->time_val; in MSS_WD_configure()
72 wdog_hw_base[wd_num]->CONTROL = (uint32_t)(config->forbidden_en << in MSS_WD_configure()
93 mss_watchdog_num_t wd_num, mss_watchdog_config_t* config in MSS_WD_get_config() argument
98 config->time_val = wdog_hw_base[wd_num]->TIME; in MSS_WD_get_config()
[all …]
Dmss_watchdog.h360 mss_watchdog_config_t* config
418 const mss_watchdog_config_t * config
/hal_microchip-latest/mpfs/drivers/mss/mss_gpio/
Dmss_gpio.c144 uint32_t config in MSS_GPIO_config() argument
149 gpio->GPIO_CFG[port_id] = config; in MSS_GPIO_config()
165 uint32_t config in MSS_GPIO_config_byte() argument
185 gpio->GPIO_CFG_BYTE[byte_num] = config; in MSS_GPIO_config_byte()
196 uint32_t config in MSS_GPIO_config_all() argument
199 gpio->GPIO_CFG_ALL = config; in MSS_GPIO_config_all()
249 uint32_t config; in MSS_GPIO_drive_inout() local
260 config = gpio->GPIO_CFG[port_id]; in MSS_GPIO_drive_inout()
261 config |= OUTPUT_BUFFER_ENABLE_MASK; in MSS_GPIO_drive_inout()
262 gpio->GPIO_CFG[port_id] = config; in MSS_GPIO_drive_inout()
[all …]
Dmss_gpio.h504 uint32_t config
615 uint32_t config
668 uint32_t config
/hal_microchip-latest/mpfs/drivers/mss/mss_qspi/
Dmss_qspi.c48 const mss_qspi_config_t* config in MSS_QSPI_configure() argument
51 QSPI->CONTROL = (uint32_t)(config->sample << CTRL_SAMPLE) | in MSS_QSPI_configure()
52 (uint32_t)(config->io_format << CTRL_QMODE0) | in MSS_QSPI_configure()
53 (uint32_t)(config->clk_div << CTRL_CLKRATE) | in MSS_QSPI_configure()
54 (uint32_t)(config->xip << CTRL_XIP) | in MSS_QSPI_configure()
55 (uint32_t)(config->xip_addr << CTRL_XIPADDR) | in MSS_QSPI_configure()
56 (uint32_t)(config->spi_mode << CTRL_CLKIDL) | in MSS_QSPI_configure()
65 mss_qspi_config_t* config in MSS_QSPI_get_config() argument
72 config->spi_mode = ((reg & CTRL_CLKIDL_MASK) >> CTRL_CLKIDL); in MSS_QSPI_get_config()
76 config->io_format = (mss_qspi_io_format)reg; in MSS_QSPI_get_config()
[all …]
Dmss_qspi.h482 const mss_qspi_config_t* config
506 mss_qspi_config_t* config
/hal_microchip-latest/scripts/
Dpic32cxsgpinctrl.py249 config = yaml.load(open(entry), Loader=yaml.Loader)
251 model = config["model"]
252 family = config["family"]
253 fmap = config["map"]
254 series = config["series"]
255 variants = config["variants"]
256 has_rev = "revisions" in config.keys()
257 pins = config["pins"]
263 rev = config["revisions"].get(serie) if has_rev else None
Dpic32pinctrl.py245 config = yaml.load(open(entry), Loader=yaml.Loader)
247 model = config["model"]
248 family = config["family"]
249 fmap = config["map"]
250 series = config["series"]
251 variants = config["variants"]
252 has_rev = "revisions" in config.keys()
253 pins = config["pins"]
259 rev = config["revisions"].get(serie) if has_rev else None
/hal_microchip-latest/mpfs/drivers/fpga_ip/CoreGPIO/
Dcore_gpio.c83 uint32_t config in GPIO_config() argument
92 HW_set_32bit_reg( cfg_reg_addr, config ); in GPIO_config()
101 HAL_ASSERT( HW_get_32bit_reg( cfg_reg_addr ) == config ); in GPIO_config()
335 uint32_t config; in GPIO_drive_inout() local
348 config = HW_get_8bit_reg( cfg_reg_addr ); in GPIO_drive_inout()
349 config |= OUTPUT_BUFFER_ENABLE_MASK; in GPIO_drive_inout()
350 HW_set_8bit_reg( cfg_reg_addr, config ); in GPIO_drive_inout()
359 config = HW_get_8bit_reg( cfg_reg_addr ); in GPIO_drive_inout()
360 config |= OUTPUT_BUFFER_ENABLE_MASK; in GPIO_drive_inout()
361 HW_set_8bit_reg( cfg_reg_addr, config ); in GPIO_drive_inout()
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Dcore_gpio.h313 uint32_t config
/hal_microchip-latest/mec5/drivers/
Dmec_uart.c285 static void prog_cfg1(struct mec_uart_regs *regs, uint32_t config, uint32_t extclk_hz) in prog_cfg1() argument
293 if (config & MEC_BIT(MEC5_UART_CFG_RESET_HOST_POS)) { in prog_cfg1()
297 if (config & MEC_BIT(MEC5_UART_CFG_INVERT_LINES_POS)) { in prog_cfg1()
339 static void prog_word_len(struct mec_uart_regs *regs, uint32_t config) in prog_word_len() argument
341 uint32_t val = ((config & MEC5_UART_CFG_WORD_LEN_MSK) >> MEC5_UART_CFG_WORD_LEN_POS); in prog_word_len()
347 static void prog_parity(struct mec_uart_regs *regs, uint32_t config) in prog_parity() argument
349 uint32_t val = ((config & MEC5_UART_CFG_PARITY_MSK) >> MEC5_UART_CFG_PARITY_POS); in prog_parity()
355 static void prog_stop_bits(struct mec_uart_regs *regs, uint32_t config) in prog_stop_bits() argument
357 if (config & MEC_BIT(MEC5_UART_CFG_STOP_BITS_POS)) { in prog_stop_bits()
365 static void prog_fifo(struct mec_uart_regs *regs, uint32_t config) in prog_fifo() argument
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Dmec_gpio.c367 int mec_hal_gpio_get_config(uint32_t pin, uint32_t *config) in mec_hal_gpio_get_config() argument
374 if (!config) { in mec_hal_gpio_get_config()
378 *config = MEC_GPIO->CTRL[pin] & 0xffffu; in mec_hal_gpio_get_config()
537 static uint32_t pull_config(uint32_t config) in pull_config() argument
541 switch (config & MEC5_GPIO_CFG_PULL_MSK) { in pull_config()
558 static uint32_t pwrgate_config(uint32_t config) in pwrgate_config() argument
562 switch (config & MEC5_GPIO_CFG_PWR_GATE_MSK) { in pwrgate_config()
576 static uint32_t idet_config(uint32_t config) in idet_config() argument
580 switch (config & MEC5_GPIO_CFG_IDET_POS) { in idet_config()
615 int mec_hal_gpio_pin_config(uint32_t pin, uint32_t config) in mec_hal_gpio_pin_config() argument
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Dmec_ecs.c112 void mec_hal_ecs_analog_comparator_config(uint32_t config) in mec_hal_ecs_analog_comparator_config() argument
117 if (config & MEC_ACMP_CFG_DS0) { in mec_hal_ecs_analog_comparator_config()
121 if (config & MEC_ACMP_CFG_DS1) { in mec_hal_ecs_analog_comparator_config()
130 if (config & MEC_ACMP_CFG_EN0) { in mec_hal_ecs_analog_comparator_config()
133 if (config & MEC_ACMP_CFG_LOCK0) { in mec_hal_ecs_analog_comparator_config()
136 if (config & MEC_ACMP_CFG_EN1) { in mec_hal_ecs_analog_comparator_config()
Dmec_i2c.c165 static void i2c_config(struct mec_i2c_smb_ctx *ctx, struct mec_i2c_smb_cfg *config, in i2c_config() argument
172 base->CONFIG = (((uint32_t)config->port << MEC_I2C_SMB_CONFIG_PORT_SEL_Pos) in i2c_config()
183 base->OWN_ADDR = config->target_addr2; in i2c_config()
184 base->OWN_ADDR = (base->OWN_ADDR << 8) | config->target_addr1; in i2c_config()
186 if (config->cfg_flags & MEC_I2C_SMB_CFG_CUST_FREQ) { in i2c_config()
189 i2c_timing(base, &freq_cfg_dflt[config->std_freq]); in i2c_config()
226 int mec_hal_i2c_smb_init(struct mec_i2c_smb_ctx *ctx, struct mec_i2c_smb_cfg *config, in mec_hal_i2c_smb_init() argument
237 if (!info || !config) { in mec_hal_i2c_smb_init()
243 if (config->cfg_flags & MEC_I2C_SMB_CFG_PRESERVE_TARGET_ADDRS) { in mec_hal_i2c_smb_init()
245 config->target_addr1 = (uint8_t)(own_addrs & 0x7fu); in mec_hal_i2c_smb_init()
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Dmec_espi_vw.c603 uint8_t src_idx, uint8_t host_index, uint32_t config) in mec_hal_espi_vw_ct_config() argument
613 if (config & MEC_BIT(MEC_ESPI_VW_CFG_RSTSRC_DO_POS)) { in mec_hal_espi_vw_ct_config()
614 temp = (((uint32_t)config & MEC_ESPI_VW_CFG_RSTSRC_MSK) >> MEC_ESPI_VW_CFG_RSTSRC_POS); in mec_hal_espi_vw_ct_config()
619 if (config & MEC_BIT(MEC_ESPI_VW_CFG_RSTVAL_DO_POS)) { in mec_hal_espi_vw_ct_config()
620 temp = (((uint32_t)config & MEC_ESPI_VW_CFG_RSTVAL_MSK) >> MEC_ESPI_VW_CFG_RSTVAL_POS); in mec_hal_espi_vw_ct_config()
626 if (config & MEC_BIT(MEC_ESPI_VW_CFG_IRQSEL_DO_POS)) { in mec_hal_espi_vw_ct_config()
629 uint32_t val = ((config >> MEC_ESPI_VW_CFG_IRQSEL_POS) & MEC_ESPI_VW_CFG_IRQSEL_MSK0); in mec_hal_espi_vw_ct_config()
793 uint8_t src_idx, uint8_t host_index, uint32_t config) in mec_hal_espi_vw_tc_config() argument
803 if (config & MEC_BIT(MEC_ESPI_VW_CFG_RSTSRC_DO_POS)) { in mec_hal_espi_vw_tc_config()
804 temp = (((uint32_t)config & MEC_ESPI_VW_CFG_RSTSRC_MSK) >> MEC_ESPI_VW_CFG_RSTSRC_POS); in mec_hal_espi_vw_tc_config()
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Dmec_i3c.c499 void MEC_HAL_I3C_Enable(struct mec_i3c_ctx *ctx, uint8_t address, uint8_t config) in MEC_HAL_I3C_Enable() argument
507 if (sbit_MODE_TARGET & config) { in MEC_HAL_I3C_Enable()
514 if (sbit_HOTJOIN_DISABLE & config) { in MEC_HAL_I3C_Enable()
516 if (sbit_MODE_TARGET & config) { in MEC_HAL_I3C_Enable()
526 if (!(sbit_MODE_TARGET & config)) { in MEC_HAL_I3C_Enable()
532 if (sbit_CONFG_ENABLE & config) { in MEC_HAL_I3C_Enable()
537 if (sbit_DMA_MODE & config) { in MEC_HAL_I3C_Enable()
Dmec_ecs_api.h75 void mec_hal_ecs_analog_comparator_config(uint32_t config);
Dmec_uart_api.h140 uint32_t config, uint32_t extclk_hz);
Dmec_gpio_api.h304 int mec_hal_gpio_pin_config(uint32_t pin, uint32_t config);
337 int mec_hal_gpio_get_config(uint32_t pin, uint32_t *config);
Dmec_i2c_api.h138 int mec_hal_i2c_smb_init(struct mec_i2c_smb_ctx *ctx, struct mec_i2c_smb_cfg *config,
/hal_microchip-latest/mpfs/boards/icicle-kit-es/platform_config/drivers_config/
Dreadme.txt2 drivers config should follow the following format:
3 platform/config/drivers/<same folder name as driver folder>/<driver name>_sw_cfg.h
5 platform/config/drivers/ddr/ddr_sw_cfg.h
/hal_microchip-latest/mpfs/mpfs_hal/
Dreadme.md29 Libero input through header files located in the config/hardware under the
78 … | | +->|multiple folders with fpga config for sw|
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_io.c351 void set_bank2_and_bank4_volts(MSSIO_CONFIG_OPTION config) in set_bank2_and_bank4_volts() argument
354 switch(config) in set_bank2_and_bank4_volts()
Dmss_io_config.h257 MSSIO_CONFIG_OPTION config
/hal_microchip-latest/mpfs/hal/
Dreadme.md28 +-->|platform +---->|config |

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