Searched refs:chan (Results 1 – 3 of 3) sorted by relevance
118 for (uint8_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in dma_clr_ia_all() local119 mec_hal_girq_clr_src(dmac_ecia_info_table[chan]); in dma_clr_ia_all()217 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_enable_mask() local218 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_enable_mask()219 dma_chan_ia_enable(chan); in mec_hal_dma_chan_ia_enable_mask()232 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_disable_mask() local233 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_disable_mask()234 dma_chan_ia_disable(chan); in mec_hal_dma_chan_ia_disable_mask()252 int mec_hal_dma_chan_init(enum mec_dmac_channel chan) in mec_hal_dma_chan_init() argument256 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_init()[all …]
122 int mec_hal_dma_chan_intr_status(enum mec_dmac_channel chan, uint32_t *status);123 int mec_hal_dma_chan_intr_status_clr(enum mec_dmac_channel chan);124 int mec_hal_dma_chan_intr_en(enum mec_dmac_channel chan, uint8_t ien);133 bool mec_hal_dma_chan_is_busy(enum mec_dmac_channel chan);135 int mec_hal_dma_chan_start(enum mec_dmac_channel chan);137 int mec_hal_dma_chan_halt(enum mec_dmac_channel chan);139 int mec_hal_dma_chan_stop(enum mec_dmac_channel chan);141 int mec_hal_dma_chan_hwfc_set(enum mec_dmac_channel chan, enum mec_dmac_hwfc_dev_id hwfc_dev,144 int mec_hal_dma_chan_dir_set(enum mec_dmac_channel chan, enum mec_dmac_dir dir);145 int mec_hal_dma_chan_dir_get(enum mec_dmac_channel chan, enum mec_dmac_dir *dir);[all …]
290 #define MEC5_QSPI_DCFG1_FLAG_DMA_TX(chan) \ argument291 (((uint32_t)(chan) & MEC5_QSPI_DCFG1_FLAG_DMA_MSK0) << MEC5_QSPI_DCFG1_FLAG_DMA_TX_POS)293 #define MEC5_QSPI_DCFG1_FLAG_DMA_RX(chan) \ argument294 (((uint32_t)(chan) & MEC5_QSPI_DCFG1_FLAG_DMA_MSK0) << MEC5_QSPI_DCFG1_FLAG_DMA_RX_POS)
