Lines Matching refs:chan
118 for (uint8_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in dma_clr_ia_all() local
119 mec_hal_girq_clr_src(dmac_ecia_info_table[chan]); in dma_clr_ia_all()
217 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_enable_mask() local
218 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_enable_mask()
219 dma_chan_ia_enable(chan); in mec_hal_dma_chan_ia_enable_mask()
232 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_disable_mask() local
233 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_disable_mask()
234 dma_chan_ia_disable(chan); in mec_hal_dma_chan_ia_disable_mask()
252 int mec_hal_dma_chan_init(enum mec_dmac_channel chan) in mec_hal_dma_chan_init() argument
256 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_init()
260 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_init()
274 int mec_hal_dma_chan_intr_status(enum mec_dmac_channel chan, uint32_t *status) in mec_hal_dma_chan_intr_status() argument
279 if (!status || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_intr_status()
283 hwsts = base->CHAN[chan].ISTATUS; in mec_hal_dma_chan_intr_status()
305 int mec_hal_dma_chan_intr_status_clr(enum mec_dmac_channel chan) in mec_hal_dma_chan_intr_status_clr() argument
309 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_intr_status_clr()
313 base->CHAN[chan].ISTATUS = MEC_DMA_CHAN_ALL_STATUS; in mec_hal_dma_chan_intr_status_clr()
314 MEC_ECIA0->GIRQ[MEC_DMAC_GIRQ_IDX].SOURCE = MEC_BIT(chan); in mec_hal_dma_chan_intr_status_clr()
319 int mec_hal_dma_chan_intr_en(enum mec_dmac_channel chan, uint8_t ien) in mec_hal_dma_chan_intr_en() argument
324 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_intr_en()
332 base->CHAN[chan].IEN = ien_val; in mec_hal_dma_chan_intr_en()
337 int mec_hal_dma_chan_start(enum mec_dmac_channel chan) in mec_hal_dma_chan_start() argument
343 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_start()
347 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_start()
360 dbg_mec_dma[chan].actv = MEC_BIT(MEC_DMA_CHAN_ACTV_EN_Pos); in mec_hal_dma_chan_start()
361 dbg_mec_dma[chan].mstart = regs->MSTART; in mec_hal_dma_chan_start()
362 dbg_mec_dma[chan].mend = regs->MEND; in mec_hal_dma_chan_start()
363 dbg_mec_dma[chan].dstart = regs->DSTART; in mec_hal_dma_chan_start()
364 dbg_mec_dma[chan].ctrl = ctrl | MEC_BIT(start_pos); in mec_hal_dma_chan_start()
365 dbg_mec_dma[chan].istatus = regs->ISTATUS; in mec_hal_dma_chan_start()
366 dbg_mec_dma[chan].ien = regs->IEN; in mec_hal_dma_chan_start()
367 dbg_mec_dma[chan].fsm = regs->FSM; in mec_hal_dma_chan_start()
376 bool mec_hal_dma_chan_is_busy(enum mec_dmac_channel chan) in mec_hal_dma_chan_is_busy() argument
380 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_is_busy()
384 if (base->CHAN[chan].CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) { in mec_hal_dma_chan_is_busy()
391 int mec_hal_dma_chan_halt(enum mec_dmac_channel chan) in mec_hal_dma_chan_halt() argument
397 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_halt()
401 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_halt()
409 int mec_hal_dma_chan_stop(enum mec_dmac_channel chan) in mec_hal_dma_chan_stop() argument
415 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_stop()
419 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_stop()
440 int mec_hal_dma_chan_hwfc_set(enum mec_dmac_channel chan, enum mec_dmac_hwfc_dev_id hwfc_dev, in mec_hal_dma_chan_hwfc_set() argument
446 if ((chan >= MEC_DMAC_CHAN_MAX) || (hwfc_dev >= MEC_DMAC_DEV_ID_MAX)) { in mec_hal_dma_chan_hwfc_set()
450 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_hwfc_set()
461 int mec_hal_dma_chan_dir_set(enum mec_dmac_channel chan, enum mec_dmac_dir dir) in mec_hal_dma_chan_dir_set() argument
465 if ((chan >= MEC_DMAC_CHAN_MAX) || (dir >= MEC_DMAC_DIR_MAX)) { in mec_hal_dma_chan_dir_set()
469 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_dir_set()
480 int mec_hal_dma_chan_dir_get(enum mec_dmac_channel chan, enum mec_dmac_dir * dir) in mec_hal_dma_chan_dir_get() argument
484 if (!dir || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_dir_get()
489 if (base->CHAN[chan].CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos)) { in mec_hal_dma_chan_dir_get()
496 int mec_hal_dma_chan_mem_set(enum mec_dmac_channel chan, uintptr_t maddr, size_t nbytes) in mec_hal_dma_chan_mem_set() argument
500 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_mem_set()
504 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_mem_set()
512 int mec_hal_dma_chan_mem_units_set(enum mec_dmac_channel chan, enum mec_dmac_unit_size unitsz) in mec_hal_dma_chan_mem_units_set() argument
517 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_mem_units_set()
521 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_mem_units_set()
536 int mec_hal_dma_chan_rem_bytes(enum mec_dmac_channel chan, uint32_t *remsz) in mec_hal_dma_chan_rem_bytes() argument
541 if (!remsz || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_rem_bytes()
545 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_rem_bytes()
559 int mec_hal_dma_chan_reload(enum mec_dmac_channel chan, uintptr_t src, uintptr_t dest, in mec_hal_dma_chan_reload() argument
564 if (chan >= MEC_DMAC_CHAN_MAX) { in mec_hal_dma_chan_reload()
568 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_reload()
571 regs->MSTART = base->CHAN[chan].MEND; in mec_hal_dma_chan_reload()
608 int mec_hal_dma_chan_cfg(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg) in mec_hal_dma_chan_cfg() argument
614 if (!cfg || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_cfg()
618 mec_hal_dma_chan_init(chan); in mec_hal_dma_chan_cfg()
624 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_cfg()
663 int mec_hal_dma_chan_cfg_get(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg) in mec_hal_dma_chan_cfg_get() argument
668 if (!cfg || (chan >= MEC_DMAC_CHAN_MAX)) { in mec_hal_dma_chan_cfg_get()
672 struct mec_dma_chan_regs *regs = &base->CHAN[chan]; in mec_hal_dma_chan_cfg_get()