1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_AC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_AC_COMPONENT_FIXUP_H_ 9 10 /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 17 } bit; /*!< Structure used for bit access */ 18 uint8_t reg; /*!< Type used for register access */ 19 } AC_CTRLA_Type; 20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 21 22 /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ 23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 24 typedef union { 25 struct { 26 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ 27 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ 28 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 29 } bit; /*!< Structure used for bit access */ 30 struct { 31 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ 32 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 33 } vec; /*!< Structure used for vec access */ 34 uint8_t reg; /*!< Type used for register access */ 35 } AC_CTRLB_Type; 36 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 37 38 /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 typedef union { 41 struct { 42 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ 43 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ 44 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 45 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ 46 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 47 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ 48 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ 49 uint16_t :2; /*!< bit: 10..11 Reserved */ 50 uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ 51 uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ 52 uint16_t :2; /*!< bit: 14..15 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 struct { 55 uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ 56 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 57 uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ 58 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 59 uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ 60 uint16_t :2; /*!< bit: 10..11 Reserved */ 61 uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ 62 uint16_t :2; /*!< bit: 14..15 Reserved */ 63 } vec; /*!< Structure used for vec access */ 64 uint16_t reg; /*!< Type used for register access */ 65 } AC_EVCTRL_Type; 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 70 typedef union { 71 struct { 72 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 73 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 74 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 75 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 76 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 77 } bit; /*!< Structure used for bit access */ 78 struct { 79 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 80 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 81 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 82 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 83 } vec; /*!< Structure used for vec access */ 84 uint8_t reg; /*!< Type used for register access */ 85 } AC_INTENCLR_Type; 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 87 88 /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 89 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 90 typedef union { 91 struct { 92 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 93 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 94 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 95 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 96 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 struct { 99 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 100 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 101 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 102 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 103 } vec; /*!< Structure used for vec access */ 104 uint8_t reg; /*!< Type used for register access */ 105 } AC_INTENSET_Type; 106 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 107 108 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { // __I to avoid read-modify-write on write-to-clear register 111 struct { 112 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ 113 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ 114 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 115 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ 116 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 struct { 119 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ 120 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 121 __I uint8_t WIN:1; /*!< bit: 4 Window x */ 122 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 123 } vec; /*!< Structure used for vec access */ 124 uint8_t reg; /*!< Type used for register access */ 125 } AC_INTFLAG_Type; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 /* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 130 typedef union { 131 struct { 132 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 133 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 134 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 135 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 136 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 137 } bit; /*!< Structure used for bit access */ 138 struct { 139 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 140 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 141 } vec; /*!< Structure used for vec access */ 142 uint8_t reg; /*!< Type used for register access */ 143 } AC_STATUSA_Type; 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 /* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ 151 uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ 152 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 153 } bit; /*!< Structure used for bit access */ 154 struct { 155 uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ 156 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 157 } vec; /*!< Structure used for vec access */ 158 uint8_t reg; /*!< Type used for register access */ 159 } AC_STATUSB_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 /* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ 163 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 164 typedef union { 165 struct { 166 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 167 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 168 } bit; /*!< Structure used for bit access */ 169 uint8_t reg; /*!< Type used for register access */ 170 } AC_DBGCTRL_Type; 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 172 173 /* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ 174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 175 typedef union { 176 struct { 177 uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ 178 uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ 179 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 180 } bit; /*!< Structure used for bit access */ 181 uint8_t reg; /*!< Type used for register access */ 182 } AC_WINCTRL_Type; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 /* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ 190 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 191 } bit; /*!< Structure used for bit access */ 192 uint8_t reg; /*!< Type used for register access */ 193 } AC_SCALER_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 198 typedef union { 199 struct { 200 uint32_t :1; /*!< bit: 0 Reserved */ 201 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 202 uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ 203 uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ 204 uint32_t :1; /*!< bit: 5 Reserved */ 205 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 206 uint32_t :1; /*!< bit: 7 Reserved */ 207 uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ 208 uint32_t :1; /*!< bit: 11 Reserved */ 209 uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ 210 uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ 211 uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ 212 uint32_t :1; /*!< bit: 18 Reserved */ 213 uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ 214 uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ 215 uint32_t :2; /*!< bit: 22..23 Reserved */ 216 uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ 217 uint32_t :1; /*!< bit: 27 Reserved */ 218 uint32_t OUT:2; /*!< bit: 28..29 Output */ 219 uint32_t :2; /*!< bit: 30..31 Reserved */ 220 } bit; /*!< Structure used for bit access */ 221 uint32_t reg; /*!< Type used for register access */ 222 } AC_COMPCTRL_Type; 223 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 224 225 /* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ 226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 227 typedef union { 228 struct { 229 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 230 uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 231 uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ 232 uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ 233 uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ 234 uint32_t :27; /*!< bit: 5..31 Reserved */ 235 } bit; /*!< Structure used for bit access */ 236 struct { 237 uint32_t :3; /*!< bit: 0.. 2 Reserved */ 238 uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ 239 uint32_t :27; /*!< bit: 5..31 Reserved */ 240 } vec; /*!< Structure used for vec access */ 241 uint32_t reg; /*!< Type used for register access */ 242 } AC_SYNCBUSY_Type; 243 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 244 245 /* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 247 typedef union { 248 struct { 249 uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ 250 uint16_t :14; /*!< bit: 2..15 Reserved */ 251 } bit; /*!< Structure used for bit access */ 252 uint16_t reg; /*!< Type used for register access */ 253 } AC_CALIB_Type; 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 255 256 /** \brief AC hardware registers */ 257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 258 typedef struct { 259 __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 260 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ 261 __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ 262 __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 263 __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 264 __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 265 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ 266 __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ 267 __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ 268 __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ 269 RoReg8 Reserved1[0x1]; 270 __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ 271 RoReg8 Reserved2[0x2]; 272 __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ 273 RoReg8 Reserved3[0x8]; 274 __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ 275 __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ 276 } Ac; 277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 278 279 #endif /* _MICROCHIP_PIC32CXSG_AC_COMPONENT_FIXUP_H_ */ 280
