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Searched refs:ASSERT (Results 1 – 23 of 23) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_l2_cache.c49 ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); in config_l2_cache()
66 ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); in config_l2_cache()
90 ASSERT((LIBERO_SETTING_WAY_MASK_DMA & scratchpad_ways_mask) == 0UL); in config_l2_cache()
91 ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 & scratchpad_ways_mask) == 0UL); in config_l2_cache()
92 ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 & scratchpad_ways_mask) == 0UL); in config_l2_cache()
93 ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 & scratchpad_ways_mask) == 0UL); in config_l2_cache()
94 ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 & scratchpad_ways_mask) == 0UL); in config_l2_cache()
95 ASSERT((LIBERO_SETTING_WAY_MASK_E51_DCACHE & scratchpad_ways_mask) == 0UL); in config_l2_cache()
96 ASSERT((LIBERO_SETTING_WAY_MASK_E51_ICACHE & scratchpad_ways_mask) == 0UL); in config_l2_cache()
97 ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_DCACHE & scratchpad_ways_mask) == 0UL); in config_l2_cache()
[all …]
Dmss_assert.h22 #define ASSERT(CHECK) macro
24 #define ASSERT(CHECK)\
Dmss_peripherals.c147 ASSERT(PERIPHERAL_SETUP[peripheral][PERIPHERAL_INDEX_OFFSET] == peripheral); in mss_config_clk_rst()
Dmss_plic.h936 ASSERT(source <= MAX_PLIC_INT); in PLIC_CompleteIRQ()
957 ASSERT(threshold <= 7); in PLIC_SetPriority_Threshold()
/hal_microchip-latest/mpfs/drivers/mss/mss_rtc/
Dmss_rtc.c95 ASSERT(prescaler <= MAX_PRESCALAR_COUNT); in MSS_RTC_init()
179 ASSERT(new_rtc_value->second >= g_rtc_min_count_lut[SECONDS]); in MSS_RTC_set_calendar_count()
180 ASSERT(new_rtc_value->second <= g_rtc_max_count_lut[SECONDS]); in MSS_RTC_set_calendar_count()
181 ASSERT(new_rtc_value->minute >= g_rtc_min_count_lut[MINUTES]); in MSS_RTC_set_calendar_count()
182 ASSERT(new_rtc_value->minute <= g_rtc_max_count_lut[MINUTES]); in MSS_RTC_set_calendar_count()
183 ASSERT(new_rtc_value->hour >= g_rtc_min_count_lut[HOURS]); in MSS_RTC_set_calendar_count()
184 ASSERT(new_rtc_value->hour <= g_rtc_max_count_lut[HOURS]); in MSS_RTC_set_calendar_count()
185 ASSERT(new_rtc_value->day >= g_rtc_min_count_lut[DAYS]); in MSS_RTC_set_calendar_count()
186 ASSERT(new_rtc_value->day <= g_rtc_max_count_lut[DAYS]); in MSS_RTC_set_calendar_count()
187 ASSERT(new_rtc_value->month >= g_rtc_min_count_lut[MONTHS]); in MSS_RTC_set_calendar_count()
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/hal_microchip-latest/mpfs/drivers/mss/mss_gpio/
Dmss_gpio.c153 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_config()
171 ASSERT(0); in MSS_GPIO_config_byte()
176 ASSERT(0); in MSS_GPIO_config_byte()
181 ASSERT(0); in MSS_GPIO_config_byte()
233 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_set_output()
282 ASSERT(0); in MSS_GPIO_drive_inout()
288 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_drive_inout()
324 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_enable_irq()
329 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_enable_irq()
366 ASSERT(0); /*LDRA warning*/ in MSS_GPIO_disable_irq()
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/hal_microchip-latest/mpfs/drivers/mss/mss_mmuart/
Dmss_uart.c247 ASSERT(pbuff != ( (uint8_t*)0)); in MSS_UART_polled_tx()
248 ASSERT(tx_size > 0u); in MSS_UART_polled_tx()
302 ASSERT(p_sz_string != ((uint8_t*)0)); in MSS_UART_polled_tx_string()
351 ASSERT(pbuff != ((uint8_t*)0)); in MSS_UART_irq_tx()
352 ASSERT(tx_size > 0u); in MSS_UART_irq_tx()
410 ASSERT(rx_buff != ((uint8_t*)0)); in MSS_UART_get_rx()
411 ASSERT(buff_size > 0u); in MSS_UART_get_rx()
440 ASSERT(MSS_UART_INVALID_IRQ > irq_mask); in MSS_UART_enable_irq()
518 ASSERT(handler != INVALID_IRQ_HANDLER ); in MSS_UART_set_rx_handler()
519 ASSERT(trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL); in MSS_UART_set_rx_handler()
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/hal_microchip-latest/mpfs/drivers/mss/mss_usb/
Dmss_usb_host.c461 ASSERT(target_addr); in MSS_USBH_write_out_pipe()
462 ASSERT(outpipe_num); in MSS_USBH_write_out_pipe()
463 ASSERT(tdev_ep_num); in MSS_USBH_write_out_pipe()
464 ASSERT(maxpktsz); in MSS_USBH_write_out_pipe()
465 ASSERT(buf); in MSS_USBH_write_out_pipe()
524 ASSERT(target_addr); in MSS_USBH_read_in_pipe()
525 ASSERT(inpipe_num); in MSS_USBH_read_in_pipe()
526 ASSERT(tdev_ep_num); in MSS_USBH_read_in_pipe()
527 ASSERT(tdev_ep_maxpktsz); in MSS_USBH_read_in_pipe()
528 ASSERT(buf); in MSS_USBH_read_in_pipe()
[all …]
Dmss_usb_device_msd.c380 ASSERT(0); //user must select FS or HS, nothing else. in usbd_msc_get_descriptor_cb()
392 ASSERT(os_conf_desc != 0u); in usbd_msc_get_descriptor_cb()
470 ASSERT(0); /*speed value can not be any other than FS or HS*/ in usbd_msc_init_cb()
551 ASSERT(g_usbd_msc_media_ops->media_get_max_lun !=0u); in usbd_msc_process_request_cb()
714 ASSERT(0); /*invalid req_type value*/ in usbd_msc_bot_fsm()
749 ASSERT(0);/*invalid req_type value*/ in usbd_msc_bot_fsm()
764 ASSERT(0); //shouldn't happen in usbd_msc_bot_fsm()
775 ASSERT(0); in usbd_msc_bot_fsm()
890 ASSERT(0); in usbd_msc_bot_fsm()
913 ASSERT(0);/*corrupt/invalid data_residue value*/ in usbd_msc_bot_fsm()
[all …]
Dmss_usb_host_msc.c354 ASSERT(0); /* Invalid CEP event */ in MSS_USBH_MSC_task()
393 ASSERT(0);/* Invalid CEP event */ in MSS_USBH_MSC_task()
476 ASSERT(0); /* phase error, reset recovery required */ in MSS_USBH_MSC_task()
738 ASSERT(0); /*Reset recovery should be tried.*/ in MSS_USBH_MSC_task()
777 ASSERT(0);/* invalid MSC class class request */ in usbh_msc_construct_class_req()
814 ASSERT(0);/* invalid cb6byte command */ in MSS_USBH_MSC_construct_cbw_cb6byte()
875 ASSERT(0);/* invalid cb10byte command */ in MSS_USBH_MSC_construct_cbw_cb10byte()
1185 ASSERT(0); /* at this point all data must be transfered */ in usbh_msc_tx_complete_cb()
1193 ASSERT(0); /* g_msc_bot_state must not be in any other state */ in usbh_msc_tx_complete_cb()
1204 ASSERT(0);/* Handling any other error. Not yet supported */ in usbh_msc_tx_complete_cb()
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Dmss_usb_host_cif.c80 ASSERT(cep->interval <= 32768u); in MSS_USBH_CIF_cep_configure()
86 ASSERT(((cep->interval != 0U) && in MSS_USBH_CIF_cep_configure()
331 ASSERT((hcep->num == MSS_USB_CEP) && in MSS_USBH_CIF_cep_write_pkt()
360 ASSERT((hcep->num == MSS_USB_CEP) && in MSS_USBH_CIF_cep_read_pkt()
366 ASSERT(received_count <= hcep->txn_length); in MSS_USBH_CIF_cep_read_pkt()
Dmss_usb_device.c421 ASSERT(err_check == USB_SUCCESS); in MSS_USBD_tx_ep_configure()
516 ASSERT(err_check == USB_SUCCESS); in MSS_USBD_rx_ep_configure()
558 ASSERT(ep_num); in MSS_USBD_rx_ep_read_prepare()
559 ASSERT(addr != 0); in MSS_USBD_rx_ep_read_prepare()
611 ASSERT(ep_num); in MSS_USBD_tx_ep_write()
612 ASSERT(addr != 0); in MSS_USBD_tx_ep_write()
935 ASSERT(0);/*in this transaction the txn_length must be SETUP_PKT_SIZE*/ in mss_usbd_cep_setup_cb()
997 ASSERT(0); in mss_usbd_cep_setup_cb()
1111 ASSERT(0); in mss_usbd_cep_rx_cb()
1315 ASSERT(0); in mss_usbd_ep_rx_cb()
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Dmss_usb_device_cif.c131 ASSERT(0); in MSS_USBD_CIF_tx_ep_configure()
176 ASSERT(0); in MSS_USBD_CIF_rx_ep_configure()
235 ASSERT(!(((uint32_t)device_ep->buf_addr) & 0x00000002)); in MSS_USBD_CIF_rx_ep_read_prepare()
Dmss_usb_common_cif.c277 ASSERT(0); in MSS_USB_CIF_handle_cep_irq()
488 ASSERT(!(((uint32_t)buf_addr) & 0x00000002U)); in MSS_USB_CIF_rx_ep_read_prepare()
541 ASSERT(!(((uint32_t)buf_addr) & 0x00000002u)); in MSS_USB_CIF_ep_write_pkt()
650 ASSERT(0); in MSS_USB_CIF_tx_ep_configure()
726 ASSERT(0); in MSS_USB_CIF_rx_ep_configure()
Dmss_usb_host_hid.c431 ASSERT(0); /*Reset recovery should be tried.*/ in MSS_USBH_HID_task()
556 ASSERT(0);/* Handling any other error. Not yet supported */ in usbh_hid_rx_cb()
/hal_microchip-latest/mpfs/drivers/mss/mss_spi/
Dmss_spi.c136 ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi1_lo)); in MSS_SPI_init()
179 ASSERT(0); in MSS_SPI_init()
198 ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi) in MSS_SPI_configure_slave_mode()
200 ASSERT(frame_bit_length <= MAX_FRAME_LENGTH); in MSS_SPI_configure_slave_mode()
245 ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi) in MSS_SPI_configure_master_mode()
247 ASSERT(slave < MSS_SPI_MAX_NB_OF_SLAVES); in MSS_SPI_configure_master_mode()
248 ASSERT(frame_bit_length <= MAX_FRAME_LENGTH); in MSS_SPI_configure_master_mode()
251 ASSERT(clk_div >= 2u); in MSS_SPI_configure_master_mode()
252 ASSERT(clk_div <= 512u); in MSS_SPI_configure_master_mode()
253 ASSERT(0u == (clk_div & 0x00000001U)); in MSS_SPI_configure_master_mode()
[all …]
/hal_microchip-latest/mpfs/hal/
Dhal_assert.h22 #define ASSERT(CHECK) macro
24 #define ASSERT(CHECK)\
46 #define HAL_ASSERT(CHECK) ASSERT(CHECK);
/hal_microchip-latest/mpfs/drivers/mss/mss_i2c/
Dmss_i2c.c115 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_init()
166 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_write()
239 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_read()
311 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_write_read()
313 ASSERT(offset_size > 0u); in MSS_I2C_write_read()
314 ASSERT(addr_offset != (const uint8_t *)0); in MSS_I2C_write_read()
315 ASSERT(read_size > 0u); in MSS_I2C_write_read()
316 ASSERT(read_buffer != (uint8_t *)0); in MSS_I2C_write_read()
393 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_get_status()
413 ASSERT((this_i2c == &g_mss_i2c0_lo) || (this_i2c == &g_mss_i2c0_hi) || in MSS_I2C_wait_complete()
[all …]
/hal_microchip-latest/mpfs/mpfs_hal/startup_gcc/
Dnewlib_stubs.c278 ASSERT(&__heap_end > &__heap_start); in _sbrk()
335 ASSERT(heap_end <= &__heap_end); in _sbrk()
Dsystem_startup.c228 ASSERT(hls->shared_mem != NULL); in u54_single_hart()
/hal_microchip-latest/mpfs/drivers/mss/mss_sys_services/
Dmss_sys_services.c625 ASSERT(!(NULL_BUFFER == p_data)); in MSS_SYS_secure_nvm_write()
626 ASSERT(!(NULL_BUFFER == p_user_key)); in MSS_SYS_secure_nvm_write()
627 ASSERT(!(snvm_module >= 221u)); in MSS_SYS_secure_nvm_write()
745 ASSERT(!(NULL_BUFFER == p_data)); in MSS_SYS_secure_nvm_read()
746 ASSERT(!(NULL_BUFFER == p_admin)); in MSS_SYS_secure_nvm_read()
747 ASSERT(!(snvm_module > 221u)); in MSS_SYS_secure_nvm_read()
749 ASSERT((data_len == 236u) || (data_len == 252u)); in MSS_SYS_secure_nvm_read()
766 ASSERT(p_user_key != NULL_BUFFER); in MSS_SYS_secure_nvm_read()
916 ASSERT(!(spi_idx == 1u)); in MSS_SYS_authenticate_iap_image()
/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dmss_ethernet_mac.c177 ASSERT(cfg != NULL_POINTER); in MSS_MAC_init()
179 ASSERT(this_mac == &g_mac0); in MSS_MAC_init()
186 …ASSERT((this_mac == &g_mac0) || (this_mac == &g_mac1) || (this_mac == &g_emac0) || (this_mac == &g… in MSS_MAC_init()
476 ASSERT(cfg != NULL_POINTER); in MSS_MAC_update_hw_address()
739 ASSERT(NULL_POINTER != cfg); in MSS_MAC_cfg_struct_def_init()
1032 ASSERT( IS_STATE(cfg->tx_edc_enable) ); in config_mac_hw()
1033 ASSERT( IS_STATE(cfg->rx_edc_enable) ); in config_mac_hw()
1034 ASSERT( IS_STATE(cfg->jumbo_frame_enable) ); in config_mac_hw()
1035 ASSERT( IS_STATE(cfg->length_field_check) ); in config_mac_hw()
1036 ASSERT( IS_STATE(cfg->append_CRC) ); in config_mac_hw()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_can/
Dmss_can.c1025 ASSERT(!"An ISR is required here if interrupts are enabled"); in External_can0_plic_IRQHandler()
1027 ASSERT(!"Unexpected MSS CAN interrupt - MSS CAN NVIC Interrupts should be \ in External_can0_plic_IRQHandler()
1038 ASSERT(!"An ISR is required here if interrupts are enabled"); in can1_IRQHandler()
1040 ASSERT(!"Unexpected MSS CAN interrupt - MSS CAN NVIC Interrupts should be \ in can1_IRQHandler()