136     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi1_lo));  in MSS_SPI_init()
179         ASSERT(0);  in MSS_SPI_init()
198     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_configure_slave_mode()
200     ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);  in MSS_SPI_configure_slave_mode()
245     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_configure_master_mode()
247     ASSERT(slave < MSS_SPI_MAX_NB_OF_SLAVES);  in MSS_SPI_configure_master_mode()
248     ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);  in MSS_SPI_configure_master_mode()
251     ASSERT(clk_div >= 2u);  in MSS_SPI_configure_master_mode()
252     ASSERT(clk_div <= 512u);  in MSS_SPI_configure_master_mode()
253     ASSERT(0u == (clk_div & 0x00000001U));  in MSS_SPI_configure_master_mode()
318     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_set_slave_select()
322     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_slave_select()
325     ASSERT(this_spi->slaves_cfg[slave].ctrl_reg != NOT_CONFIGURED);  in MSS_SPI_set_slave_select()
364     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_clear_slave_select()
368     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_clear_slave_select()
398     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_transfer_frame()
402     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_transfer_frame()
461     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_transfer_block()
465     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_transfer_block()
585     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_set_frame_rx_handler()
589     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_frame_rx_handler()
646     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_set_slave_tx_frame()
650     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_slave_tx_frame()
727     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in MSS_SPI_set_slave_block_buffers()
731     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);  in MSS_SPI_set_slave_block_buffers()
1094     ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi)   in mss_spi_isr()
1341         ASSERT(0);  in recover_from_rx_overflow()