Searched refs:CPOL (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/ |
| D | Kconfig | 9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
|
| D | README.txt | 3 In each test, both instances get identical configuration (CPOL, CPHA, bitrate, etc.).
|
| /Zephyr-latest/boards/shields/x_nucleo_wb05kn1/ |
| D | x_nucleo_wb05kn1_spi.overlay | 21 spi-cpol; /* CPOL=1 */
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_xmc4xxx.c | 196 bool CPOL = SPI_MODE_GET(settings) & SPI_MODE_CPOL; in spi_xmc4xxx_configure() local
236 if (!CPOL && !CPHA) { in spi_xmc4xxx_configure()
238 } else if (!CPOL && CPHA) { in spi_xmc4xxx_configure()
240 } else if (CPOL && !CPHA) { in spi_xmc4xxx_configure()
242 } else if (CPOL && CPHA) { in spi_xmc4xxx_configure()
|
| D | spi_sam0.c | 103 ctrla.bit.CPOL = 1; in spi_sam0_configure()
|
| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 200 input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
203 Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
204 Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
|
| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.4.rst | 964 * Support was added for using CPOL/CPHA SPI clock modes with SD cards, as
|
