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Searched refs:MISC_ISH_ECC_ERR_SRESP (Results 1 – 2 of 2) sorted by relevance

/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/
Dpm_regs.h132 #define MISC_ISH_ECC_ERR_SRESP (DMA_MISC_BASE + 0x404) macro
/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c797 write32(MISC_ISH_ECC_ERR_SRESP, 1); in handle_reset()