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/hal_infineon-latest/core-lib/include/
Dcy_utils.h84 #define CY_ASSERT_AND_RETURN(condition, value) \ argument
87 (void)(value); \
103 #define CY_ASSERT_AND_RETURN(condition, value) \ argument
108 return (value); \
233 #define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) argument
261 #define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) argument
291 #define CY_SET_REG24(addr, value) \ argument
294 (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \
295 (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \
296 (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \
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/hal_infineon-latest/core-lib/
DREADME.md11 * `CY_ASSERT`: Verifies a value and halts if invalid (if not NDEBUG)
14 * `CY_LO8`: Gets the lower 8 bits of a 16-bit value
15 * `CY_HI8`: Gets the upper 8 bits of a 16-bit value
16 * `CY_LO16`: Gets the lower 16 bits of a 32-bit value
17 * `CY_HI16`: Gets the upper 16 bits of a 32-bit value
18 * `CY_SWAP_ENDIAN16`: Swaps the byte ordering of a 16-bit value
19 * `CY_SWAP_ENDIAN32`: Swaps the byte ordering of a 32-bit value
20 * `CY_SWAP_ENDIAN64`: Swaps the byte ordering of a 64-bit value
21 * `CY_GET_REG8`: Reads the 8-bit value from the specified address
22 * `CY_SET_REG8`: Writes an 8-bit value to the specified address
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DRELEASE.md7 * CY_ASSERT: Verifies a value and halts if invalid (if not NDEBUG)
10 * CY_LO8: Gets the lower 8 bits of a 16-bit value
11 * CY_HI8: Gets the upper 8 bits of a 16-bit value
12 * CY_LO16: Gets the lower 16 bits of a 32-bit value
13 * CY_HI16: Gets the upper 16 bits of a 32-bit value
14 * CY_SWAP_ENDIAN16: Swaps the byte ordering of a 16-bit value
15 * CY_SWAP_ENDIAN32: Swaps the byte ordering of a 32-bit value
16 * CY_SWAP_ENDIAN64: Swaps the byte ordering of a 64-bit value
17 * CY_GET_REG8: Reads the 8-bit value from the specified address
18 * CY_SET_REG8: Writes an 8-bit value to the specified address
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/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c811 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value) in Cy_GPIO_SetHSIOM() argument
823 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value)); in Cy_GPIO_SetHSIOM()
866 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
930 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
1151 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) in Cy_GPIO_Write() argument
1160 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); in Cy_GPIO_Write()
1170 if(0UL == value) in Cy_GPIO_Write()
1199 if(0UL == value) in Cy_GPIO_Write()
1456 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) in Cy_GPIO_SetDrivemode() argument
1470 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value)); in Cy_GPIO_SetDrivemode()
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Dcy_seglcd.c122 static char_t NumToChar(uint32_t value);
340 static char_t NumToChar(uint32_t value) in NumToChar() argument
344 if (value < 10UL) /* For dec numbers 0...9 */ in NumToChar()
346 character = (uint32_t)'0' + value; in NumToChar()
348 else if (value < 0x10UL) /* For hex numbers A...F */ in NumToChar()
350 character = ((uint32_t)'A' - 0xAUL) + value; in NumToChar()
679 cy_en_seglcd_status_t Cy_SegLCD_WritePixel(LCD_Type * base, uint32_t pixel, bool value) in Cy_SegLCD_WritePixel() argument
690 CY_REG32_CLR_SET(*GetDataRegPtr(base, pixel), loc, value ? 1UL : 0UL); in Cy_SegLCD_WritePixel()
824 uint32_t value, in Cy_SegLCD_WriteNumber() argument
843 if ((0UL == value) && (i != position) && (!zeroes)) in Cy_SegLCD_WriteNumber()
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Dcy_systick.c47 void Cy_SysTick_SetReload(uint32_t value) in Cy_SysTick_SetReload() argument
49 CY_ASSERT_L1(CY_SYSTICK_IS_RELOAD_VALID(value)); in Cy_SysTick_SetReload()
51 SYSTICK_LOAD = (value & SysTick_LOAD_RELOAD_Msk); in Cy_SysTick_SetReload()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_gpio.h841 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
846 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
861 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
866 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
868 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
871 void Cy_GPIO_SetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
874 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
876 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
880 void Cy_GPIO_SetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
891 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
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Dcy_ctdac.h546 int32_t value; /**< Current DAC value */ member
669 __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value);
670 __STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value);
781 __STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value) in Cy_CTDAC_SetValue() argument
783 …CTDAC_CTDAC_VAL(base) = (((uint32_t)value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_M… in Cy_CTDAC_SetValue()
814 __STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value) in Cy_CTDAC_SetValueBuffered() argument
816 …CTDAC_CTDAC_VAL_NXT(base) = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL… in Cy_CTDAC_SetValueBuffered()
Dcy_csd.h703 __STATIC_INLINE void Cy_CSD_WriteReg(CSD_Type * base, uint32_t offset, uint32_t value);
706 …TATIC_INLINE void Cy_CSD_WriteBits(CSD_Type* base, uint32_t offset, uint32_t mask, uint32_t value);
747 __STATIC_INLINE void Cy_CSD_WriteReg(CSD_Type * base, uint32_t offset, uint32_t value) in Cy_CSD_WriteReg() argument
749 (* (volatile uint32_t *)((uint32_t)base + offset)) = value; in Cy_CSD_WriteReg()
821 …TATIC_INLINE void Cy_CSD_WriteBits(CSD_Type * base, uint32_t offset, uint32_t mask, uint32_t value) in Cy_CSD_WriteBits() argument
824 (* regPtr) = ((* regPtr) & ~mask) | (value & mask); in Cy_CSD_WriteBits()
Dcy_usbfs_dev_drv_reg.h125 …ATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value);
554 __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Data(USBFS_Type *base, uint32_t idx, uint32_t value) in Cy_USBFS_Dev_Drv_WriteEp0Data() argument
558 USBFS_DEV_EP0_DR(base, idx) = value; in Cy_USBFS_Dev_Drv_WriteEp0Data()
563 USBFS_DEV_EP0_DR(base, idx) = CY_USBFS_DEV_DRV_WRITE_ODD(value); in Cy_USBFS_Dev_Drv_WriteEp0Data()
587 uint32_t value; in Cy_USBFS_Dev_Drv_ReadEp0Data() local
591 value = USBFS_DEV_EP0_DR(base, idx); in Cy_USBFS_Dev_Drv_ReadEp0Data()
596 value = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP0_DR(base, idx)); in Cy_USBFS_Dev_Drv_ReadEp0Data()
599 return (value); in Cy_USBFS_Dev_Drv_ReadEp0Data()
Dcy_sar.h857 #define CY_SAR_CTRL(value) (((value) & (~CY_SAR_REG_CTRL_MASK)) == 0UL) argument
858 #define CY_SAR_SAMPLE_CTRL(value) (((value) & (~CY_SAR_REG_SAMPLE_CTRL_MASK)) == 0UL) argument
859 #define CY_SAR_SAMPLE_TIME(value) (((value) & (~CY_SAR_REG_SAMPLE_TIME_MASK)) == 0UL) argument
860 #define CY_SAR_CHAN_CONFIG(value) (((value) & (~CY_SAR_REG_CHAN_CONFIG_MASK)) == 0UL) argument
1528 uint16_t value; /**< SAR sample */ member
2487 readStruct->value = (uint16_t)_FLD2VAL(PASS_FIFO_V2_RD_DATA_RESULT, locReg); in Cy_SAR_FifoRead()
Dcy_smif_memslot.h1292 uint8_t *value,
1298 __STATIC_INLINE void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32…
1631 uint8_t *value, in ReadAnyReg() argument
1653 result = Cy_SMIF_ReceiveDataBlocking( base, value, in ReadAnyReg()
1679 static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size) in ValueToByteArray() argument
1684 byteArray[size + startPos] = (uint8_t)(value & PARAM_ID_LSB_MASK); in ValueToByteArray()
1685 value >>= PARAM_ID_MSB_OFFSET; /* Shift to get the next byte */ in ValueToByteArray()
1709 uint32_t value = 0UL; in ByteArrayToValue() local
1713 value <<= 8; in ByteArrayToValue()
1714 value |= ((uint32_t) byteArray[idx]); in ByteArrayToValue()
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/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/bus_protocols/
Dwhd_bus.c30 uint8_t value_length, uint32_t value) in whd_bus_write_reg_value() argument
33 return whd_bus_write_backplane_value(whd_driver, address, value_length, value); in whd_bus_write_reg_value()
38 uint8_t value_length, uint8_t *value) in whd_bus_read_reg_value() argument
41 return whd_bus_read_backplane_value(whd_driver, address, value_length, value); in whd_bus_read_reg_value()
136 uint32_t value) in whd_bus_write_backplane_value() argument
138 …hd_driver->bus_if->whd_bus_write_backplane_value_fptr(whd_driver, address, register_length, value); in whd_bus_write_backplane_value()
142 uint8_t *value) in whd_bus_read_backplane_value() argument
144 …whd_driver->bus_if->whd_bus_read_backplane_value_fptr(whd_driver, address, register_length, value); in whd_bus_read_backplane_value()
148 uint8_t value_length, uint8_t *value) in whd_bus_read_register_value() argument
150 …iver->bus_if->whd_bus_read_register_value_fptr(whd_driver, function, address, value_length, value); in whd_bus_read_register_value()
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Dwhd_bus_m2m_protocol.c58 #define REGISTER_WRITE_WITH_BARRIER(type, address, value) \ argument
59 do {*(volatile type *)(address) = (type)(value); \
93 uint8_t register_length, uint32_t value);
95 uint8_t *value);
97 … uint32_t address, uint8_t value_length, uint32_t value);
99 … uint32_t address, uint8_t value_length, uint8_t *value);
320 uint8_t register_length, uint32_t value) in whd_bus_m2m_write_backplane_value() argument
327 REGISTER_WRITE_WITH_BARRIER(uint32_t, address, value); in whd_bus_m2m_write_backplane_value()
331 REGISTER_WRITE_WITH_BARRIER(uint16_t, address, value); in whd_bus_m2m_write_backplane_value()
335 REGISTER_WRITE_WITH_BARRIER(uint8_t, address, value); in whd_bus_m2m_write_backplane_value()
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Dwhd_bus_protocol_interface.h78 uint8_t value_length, uint32_t value);
80 uint8_t value_length, uint8_t *value);
96 uint32_t value);
98 uint8_t *value);
100 uint8_t value_length, uint32_t value);
102 uint8_t value_length, uint8_t *value);
120 extern whd_result_t whd_bus_set_flow_control(whd_driver_t whd_driver, uint8_t value);
Dwhd_bus_sdio_protocol.h88 uint32_t value; member
119 uint32_t value; member
168 uint8_t register_length, uint32_t value);
170 uint8_t register_length, uint8_t *value);
172 … uint32_t address, uint8_t value_length, uint32_t value);
174 … uint32_t address, uint8_t value_length, uint8_t *value);
Dwhd_bus_spi_protocol.h74 … uint32_t address, uint8_t value_length, uint32_t value);
76 … uint32_t address, uint8_t value_length, uint8_t *value);
78 uint8_t register_length, uint32_t value);
80 uint8_t *value);
Dwhd_bus.h51 uint8_t register_length, uint32_t value);
53 uint8_t register_length, uint8_t *value);
56 … uint32_t address, uint8_t value_length, uint32_t value);
58 … uint32_t address, uint8_t value_length, uint8_t *value);
Dwhd_bus_sdio_protocol.c107 whd_bus_function_t function, uint32_t address, uint8_t value,
771 uint32_t value) in whd_bus_sdio_write_backplane_value() argument
781 (uint8_t *)&value, RESPONSE_NEEDED) ); in whd_bus_sdio_write_backplane_value()
787 uint8_t *value) in whd_bus_sdio_read_backplane_value() argument
789 *value = 0; in whd_bus_sdio_read_backplane_value()
797 …RN(whd_bus_sdio_transfer(whd_driver, BUS_READ, BACKPLANE_FUNCTION, address, register_length, value, in whd_bus_sdio_read_backplane_value()
804 uint8_t value_length, uint32_t value) in whd_bus_sdio_write_register_value() argument
806 …rn whd_bus_sdio_transfer(whd_driver, BUS_WRITE, function, address, value_length, (uint8_t *)&value, in whd_bus_sdio_write_register_value()
877 whd_bus_function_t function, uint32_t address, uint8_t value, in whd_bus_sdio_cmd52() argument
883 arg.value = 0; in whd_bus_sdio_cmd52()
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/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_trng_impl.h57 uint32_t value; in _cyhal_trng_generate_internal() local
61 obj->base, CYHAL_GARO31_INITSTATE, CYHAL_FIRO31_INITSTATE, MAX_TRNG_BIT_SIZE, &value); in _cyhal_trng_generate_internal()
64 obj->base, MAX_TRNG_BIT_SIZE, &value); in _cyhal_trng_generate_internal()
69 return value; in _cyhal_trng_generate_internal()
Dcyhal_gpio_impl.h95 __STATIC_INLINE void cyhal_gpio_write_internal(cyhal_gpio_t pin, bool value) in cyhal_gpio_write_internal() argument
97 Cy_GPIO_Write(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), value); in cyhal_gpio_write_internal()
100 #define cyhal_gpio_write(pin, value) cyhal_gpio_write_internal(pin, value) argument
/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/include/
Dwhd_types_int.h141 #define WHD_WRITE_16(pointer, value) (*( (uint16_t *)pointer ) = value) argument
142 #define WHD_WRITE_32(pointer, value) (*( (uint32_t *)pointer ) = value) argument
360 uint32_t whd_wifi_get_iovar_value(whd_interface_t ifp, const char *iovar, uint32_t *value);
363 uint32_t whd_wifi_set_iovar_value(whd_interface_t ifp, const char *iovar, uint32_t value);
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_dac.c106 .value = 0,
431 void cyhal_dac_write(const cyhal_dac_t *obj, uint16_t value) in cyhal_dac_write() argument
433 uint16_t scaled_value = value / _CYHAL_DAC_VALUE_SCALING_FACTOR; in cyhal_dac_write()
437 cy_rslt_t cyhal_dac_write_mv(const cyhal_dac_t *obj, uint16_t value) in cyhal_dac_write_mv() argument
459 uint32_t count = (value << 12) / reference_voltage_mv; in cyhal_dac_write_mv()
468 uint16_t value = (uint16_t)obj->base_dac->CTDAC_VAL; in cyhal_dac_read() local
469 uint16_t scaled_value = value * _CYHAL_DAC_VALUE_SCALING_FACTOR; in cyhal_dac_read()
/hal_infineon-latest/mtb-pdl-cat1/drivers/third_party/ethernet/include/
Dcps_v2.h109 extern void CPS_UncachedWrite8(volatile uint8_t* address, uint8_t value);
116 extern void CPS_UncachedWrite16(volatile uint16_t* address, uint16_t value);
123 extern void CPS_UncachedWrite32(volatile uint32_t* address, uint32_t value);
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_hrpwm.h2071 __STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV2(XMC_HRPWM_CSG_t *const csg, uint32_t value) in XMC_HRPWM_CSG_UpdateDACRefDSV2() argument
2074 csg->DSV2 = value & HRPWM0_CSG_DSV2_DSV2_Msk; in XMC_HRPWM_CSG_UpdateDACRefDSV2()
2089 __STATIC_INLINE void XMC_HRPWM_CSG_UpdateBlankingValue(XMC_HRPWM_CSG_t *const csg, uint8_t value) in XMC_HRPWM_CSG_UpdateBlankingValue() argument
2092 csg->BLV = (uint32_t) value; in XMC_HRPWM_CSG_UpdateBlankingValue()
2135 __STATIC_INLINE void XMC_HRPWM_CSG_UpdatePulseClk(XMC_HRPWM_CSG_t *const csg, uint32_t value) in XMC_HRPWM_CSG_UpdatePulseClk() argument
2138 csg->SPC = value & HRPWM0_CSG_SPC_SPSWV_Msk; in XMC_HRPWM_CSG_UpdatePulseClk()
2158 __STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV1(XMC_HRPWM_CSG_t *const csg, uint32_t value) in XMC_HRPWM_CSG_UpdateDACRefDSV1() argument
2161 csg->SDSV1 = value & HRPWM0_CSG_SDSV1_SDSV1_Msk; in XMC_HRPWM_CSG_UpdateDACRefDSV1()

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