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/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_usbfs_dev_drv.h1358 #define CY_USBFS_DEV_DRV_SET_SOF_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL, l… argument
1360 #define CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_… argument
1362 #define CY_USBFS_DEV_DRV_SET_EP0_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL, l… argument
1364 #define CY_USBFS_DEV_DRV_SET_LPM_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL, l… argument
1366 #define CY_USBFS_DEV_DRV_SET_RESUME_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL… argument
1368 #define CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL… argument
1370 #define CY_USBFS_DEV_DRV_SET_EP1_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL, l… argument
1372 #define CY_USBFS_DEV_DRV_SET_EP2_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL, l… argument
1374 #define CY_USBFS_DEV_DRV_SET_EP3_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL, l… argument
1376 #define CY_USBFS_DEV_DRV_SET_EP4_LVL(level) _VAL2FLD(USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL, l… argument
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Dcy_scb_common.h376 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
382 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
840 #define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base)) argument
893 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level) in Cy_SCB_SetRxFifoLevel() argument
895 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)); in Cy_SCB_SetRxFifoLevel()
897 CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level); in Cy_SCB_SetRxFifoLevel()
997 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level) in Cy_SCB_SetTxFifoLevel() argument
999 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)); in Cy_SCB_SetTxFifoLevel()
1001 CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level); in Cy_SCB_SetTxFifoLevel()
Dcy_smif.h1400 __STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
1401 __STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
1629 __STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level) in Cy_SMIF_SetTxFifoTriggerLevel() argument
1631 CY_ASSERT_L2(level <= CY_SMIF_MAX_TX_TR_LEVEL); in Cy_SMIF_SetTxFifoTriggerLevel()
1632 SMIF_TX_DATA_FIFO_CTL(base) = level; in Cy_SMIF_SetTxFifoTriggerLevel()
1651 __STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level) in Cy_SMIF_SetRxFifoTriggerLevel() argument
1653 CY_ASSERT_L2(level <= CY_SMIF_MAX_RX_TR_LEVEL); in Cy_SMIF_SetRxFifoTriggerLevel()
1654 SMIF_RX_DATA_FIFO_CTL(base) = level; in Cy_SMIF_SetRxFifoTriggerLevel()
Dcy_ctb.h468 #define CY_CTB_COMPLEVEL(level) (((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE) || ((le… argument
1088 …ig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_by…
Dcy_sar.h861 #define CY_SAR_IS_FIFO_LEVEL_VALID(level) ((level) <= PASS_FIFO_V2_LEVEL_LEVEL_Msk) argument
1453 …uint32_t level; /**< A trigger (and optional interrupt) event … member
1691 __STATIC_INLINE void Cy_SAR_FifoSetLevel(const SAR_Type *base, uint32_t level);
2717 __STATIC_INLINE void Cy_SAR_FifoSetLevel(const SAR_Type *base, uint32_t level) in Cy_SAR_FifoSetLevel() argument
2723 uint32_t locLevel = level - 1UL; /* Convert the user value into the machine value */ in Cy_SAR_FifoSetLevel()
Dcy_scb_uart.h604 __STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level);
1055 __STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level) in Cy_SCB_UART_SetRtsFifoLevel() argument
1057 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)); in Cy_SCB_UART_SetRtsFifoLevel()
1059 CY_REG32_CLR_SET(SCB_UART_FLOW_CTRL(base), SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, level); in Cy_SCB_UART_SetRtsFifoLevel()
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_bccu.c210 …SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level) in XMC_BCCU_ConcurrentSetOutputPassiveLevel() argument
215 bccu->CHOCON |= (chan_mask * (uint32_t)level); in XMC_BCCU_ConcurrentSetOutputPassiveLevel()
318 void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level) in XMC_BCCU_SetGlobalDimmingLevel() argument
320 …XMC_ASSERT("XMC_BCCU_SetGlobalDimmingLevel: Invalid global dimming level", (level <= BCCU_GLOBDIM_… in XMC_BCCU_SetGlobalDimmingLevel()
322 bccu->GLOBDIM = level; in XMC_BCCU_SetGlobalDimmingLevel()
348 …U_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level) in XMC_BCCU_SetOutputPassiveLevel() argument
352 bccu->CHOCON |= ((uint32_t)level << chan_no); in XMC_BCCU_SetOutputPassiveLevel()
472 void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level) in XMC_BCCU_CH_SetPackerOffCompare() argument
475 channel->PKCMP |= level; in XMC_BCCU_CH_SetPackerOffCompare()
481 void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level) in XMC_BCCU_CH_SetPackerOnCompare() argument
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Dxmc_ccu4.c681 ((ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
682 (ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
690 ((ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
691 (ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
707 ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS2_EV1LM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
711 ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS2_EV2LM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
747 ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS_EV1LM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
751 ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS_EV2LM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
788 ((config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU4_SLICE_ConfigureEvent()
789 (config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU4_SLICE_ConfigureEvent()
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Dxmc_ccu8.c728 ((ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
729 (ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
737 ((ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
738 (ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
755 ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS2_EV1LM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
759 ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS2_EV2LM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
794 ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS_EV1LM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
798 ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS_EV2LM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
835 ((config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ in XMC_CCU8_SLICE_ConfigureEvent()
836 (config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); in XMC_CCU8_SLICE_ConfigureEvent()
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Dxmc_hrpwm.c472 reg |= ((uint32_t) config->level) << HRPWM0_CSG_PLC_PLCL_Pos; in XMC_HRPWM_CSG_SelClampingInput()
529 csg->IES |= ((uint32_t)config->level) << HRPWM0_CSG_IES_SVLS_Pos; in XMC_HRPWM_CSG_DACRefValSwitchingConfig()
/hal_infineon-latest/btstack-integration/COMPONENT_BTSS-IPC/platform/common/
Dcybt_platform_trace.c72 cybt_trace_level_t level in cybt_platform_set_trace_level() argument
76 if(CYBT_TRACE_ID_MAX < level) in cybt_platform_set_trace_level()
83 trace_cb.trace_level[id] = level; in cybt_platform_set_trace_level()
91 trace_cb.trace_level[idx] = level; in cybt_platform_set_trace_level()
96 UNUSED_VARIABLE(level); in cybt_platform_set_trace_level()
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_gpio.h103 #define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \ argument
104 (level == XMC_GPIO_OUTPUT_LEVEL_HIGH))
229 …SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level) in XMC_GPIO_SetOutputLevel() argument
232 XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); in XMC_GPIO_SetOutputLevel()
234 port->OMR = (uint32_t)level << pin; in XMC_GPIO_SetOutputLevel()
Dxmc_bccu.h889 …etOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level);
1086 void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level);
1237 …_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level);
1506 void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1523 void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1863 void XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level);
Dxmc1_flash.h438 __STATIC_INLINE void XMC_FLASH_SetHardReadLevel(XMC_FLASH_HARDREAD_LEVEL_t level) in XMC_FLASH_SetHardReadLevel() argument
441 NVM->NVMCONF |= (uint16_t)(level<< (uint16_t)NVM_NVMCONF_HRLEV_Pos); in XMC_FLASH_SetHardReadLevel()
/hal_infineon-latest/
DReadme.txt15 - mtb-hal-cat1 - the Hardware Abstraction Layer (HAL) provides a high-level
18 on ease-of-use and portability means the HAL does not expose all of the low-level
23 - mtb-pdl-cat1 - MTB CAT1 PDL provides low level device drivers for CAT1A family
29 - XMCLib - The XMC Peripheral Library (XMCLib) consists of low-level drivers for
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_scb_ezi2c.c998 uint32_t level; in UpdateRxFifoLevel() local
1004 level = (bufSize - fifoSize); in UpdateRxFifoLevel()
1005 level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL; in UpdateRxFifoLevel()
1014 level = ((bufSize == 0UL) ? (0UL) : (bufSize - 1UL)); in UpdateRxFifoLevel()
1018 Cy_SCB_SetRxFifoLevel(base, level); in UpdateRxFifoLevel()
Dcy_scb_i2c.c2499 uint32_t level = 0UL; in SlaveHandleAddress() local
2519 level = (context->slaveRxBufferSize - fifoSize); in SlaveHandleAddress()
2520 level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL; in SlaveHandleAddress()
2525 level = (context->slaveRxBufferSize - 1UL); in SlaveHandleAddress()
2536 Cy_SCB_SetRxFifoLevel(base, level); in SlaveHandleAddress()
2566 uint32_t level; in SlaveHandleDataReceive() local
2581 level = context->slaveRxBufferSize - fifoSize; in SlaveHandleDataReceive()
2582 level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL; in SlaveHandleDataReceive()
2588 … level = (context->slaveRxBufferSize == 0UL) ? (0UL) : (context->slaveRxBufferSize - 1UL); in SlaveHandleDataReceive()
2593 Cy_SCB_SetRxFifoLevel(base, level); in SlaveHandleDataReceive()
Dcy_ctb.c1384 …ig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_by… in Cy_CTB_CompSetConfig() argument
1387 CY_ASSERT_L3(CY_CTB_COMPLEVEL(level)); in Cy_CTB_CompSetConfig()
1396 … CTBM_OA_RES0_CTRL(base) = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; in Cy_CTB_CompSetConfig()
1402 … CTBM_OA_RES1_CTRL(base) = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; in Cy_CTB_CompSetConfig()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_scb_common.c697 cy_rslt_t _cyhal_scb_set_fifo_level(CySCB_Type *base, cyhal_scb_fifo_type_t type, uint16_t level) in _cyhal_scb_set_fifo_level() argument
699 if(!CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)) in _cyhal_scb_set_fifo_level()
705 SCB_RX_FIFO_CTRL(base) |= _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level); in _cyhal_scb_set_fifo_level()
712 SCB_TX_FIFO_CTRL(base) |= _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level); in _cyhal_scb_set_fifo_level()
/hal_infineon-latest/mtb-hal-cat1/
DREADME.md5 …level interface to configure and use hardware blocks on ModusToolbox™ MCUs. It is a generic interf…
7 To use code from the HAL, the specific driver header file can be included or the top level `cyhal.h…
25 …ed use cases. For example, if a block instance will be managed by a lower-level API (for example, …
28 …t can be used to control when the application can go to sleep at a global level. Additionally, eac…
45 …he driver header are not a comprehensive list; in less common cases a low-level, implementation-sp…
DRELEASE.md56 * Fix uninitialized UART RTS FIFO level on CAT1C devices.
88 1. Fix level/edge nature of the source not being honored in `cyhal_*_connect_digital`.
102 …able_output updated to require a new argument to specify whether the signal is level or edge based.
141 * Fixed issues with level trigger signals to the DMA driver
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_scb_common.h170 cy_rslt_t _cyhal_scb_set_fifo_level(CySCB_Type *base, cyhal_scb_fifo_type_t type, uint16_t level);
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_uart.h459 cy_rslt_t cyhal_uart_set_fifo_level(cyhal_uart_t *obj, cyhal_uart_fifo_type_t type, uint16_t level);
Dcyhal_spi.h446 cy_rslt_t cyhal_spi_set_fifo_level(cyhal_spi_t *obj, cyhal_spi_fifo_type_t type, uint16_t level);
/hal_infineon-latest/mtb-template-cat1/
DREADME.md28 …ill cause the BSP to include the applicable header file and to initialize the system level drivers.

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