Home
last modified time | relevance | path

Searched refs:ctl (Results 1 – 9 of 9) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_dmac.h360 uint32_t ctl; /*!< 0x00000000 Descriptor control */ member
376 uint32_t ctl; member
384 uint32_t ctl; member
392 uint32_t ctl; member
401 uint32_t ctl; member
749 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_INTR_TYPE, interruptType); in Cy_DMAC_Descriptor_SetInterruptType()
771 return((cy_en_dmac_trigger_type_t) _FLD2VAL(DMAC_CH_V2_DESCR_CTL_INTR_TYPE, descriptor->ctl)); in Cy_DMAC_Descriptor_GetInterruptType()
795 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, triggerInType); in Cy_DMAC_Descriptor_SetTriggerInType()
817 return((cy_en_dmac_trigger_type_t) _FLD2VAL(DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, descriptor->ctl)); in Cy_DMAC_Descriptor_GetTriggerInType()
841 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, triggerOutType); in Cy_DMAC_Descriptor_SetTriggerOutType()
[all …]
Dcy_dma.h435 uint32_t ctl; /*!< 0x00000000 Descriptor control */ member
903 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType); in Cy_DMA_Descriptor_SetInterruptType()
925 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl)); in Cy_DMA_Descriptor_GetInterruptType()
949 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType); in Cy_DMA_Descriptor_SetTriggerInType()
971 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl)); in Cy_DMA_Descriptor_GetTriggerInType()
995 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType); in Cy_DMA_Descriptor_SetTriggerOutType()
1017 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl)); in Cy_DMA_Descriptor_GetTriggerOutType()
1041 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize); in Cy_DMA_Descriptor_SetDataSize()
1063 return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl)); in Cy_DMA_Descriptor_GetDataSize()
1087 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize); in Cy_DMA_Descriptor_SetSrcTransferSize()
[all …]
Dcy_axidmac.h296 uint32_t ctl; /*!< Descriptor control */ member
313 uint32_t ctl; /*!< Descriptor control */ member
322 uint32_t ctl; /*!< Descriptor control */ member
933 CY_REG32_CLR_SET(descriptor->ctl, AXI_DMAC_CH_DESCR_CTL_INTR_TYPE, interruptType); in Cy_AXIDMAC_Descriptor_SetInterruptType()
956 … return((cy_en_axidmac_trigger_type_t) _FLD2VAL(AXI_DMAC_CH_DESCR_CTL_INTR_TYPE, descriptor->ctl)); in Cy_AXIDMAC_Descriptor_GetInterruptType()
980 CY_REG32_CLR_SET(descriptor->ctl, AXI_DMAC_CH_DESCR_CTL_TR_IN_TYPE, triggerInType); in Cy_AXIDMAC_Descriptor_SetTriggerInType()
1003 …return((cy_en_axidmac_trigger_type_t) _FLD2VAL(AXI_DMAC_CH_DESCR_CTL_TR_IN_TYPE, descriptor->ctl)); in Cy_AXIDMAC_Descriptor_GetTriggerInType()
1027 CY_REG32_CLR_SET(descriptor->ctl, AXI_DMAC_CH_DESCR_CTL_TR_OUT_TYPE, triggerOutType); in Cy_AXIDMAC_Descriptor_SetTriggerOutType()
1050 …eturn((cy_en_axidmac_trigger_type_t) _FLD2VAL(AXI_DMAC_CH_DESCR_CTL_TR_OUT_TYPE, descriptor->ctl)); in Cy_AXIDMAC_Descriptor_GetTriggerOutType()
1076 CY_REG32_CLR_SET(descriptor->ctl, AXI_DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT, retrigger); in Cy_AXIDMAC_Descriptor_SetRetrigger()
[all …]
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_axidmac.c57 descriptor->ctl = in Cy_AXIDMAC_Descriptor_Init()
111 descriptor->ctl = 0UL; in Cy_AXIDMAC_Descriptor_DeInit()
229 …witch((cy_en_axidmac_descriptor_type_t)_FLD2VAL(AXI_DMAC_CH_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) in Cy_AXIDMAC_Descriptor_SetNextDescriptor()
271 …witch((cy_en_axidmac_descriptor_type_t)_FLD2VAL(AXI_DMAC_CH_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) in Cy_AXIDMAC_Descriptor_GetNextDescriptor()
324 CY_REG32_CLR_SET(descriptor->ctl, AXI_DMAC_CH_DESCR_CTL_DESCR_TYPE, descriptorType); in Cy_AXIDMAC_Descriptor_SetDescriptorType()
Dcy_dmac.c79 descriptor->ctl = in Cy_DMAC_Descriptor_Init()
148 descriptor->ctl = 0UL; in Cy_DMAC_Descriptor_DeInit()
352 switch((cy_en_dmac_descriptor_type_t)_FLD2VAL(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) in Cy_DMAC_Descriptor_SetNextDescriptor()
406 switch((cy_en_dmac_descriptor_type_t)_FLD2VAL(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) in Cy_DMAC_Descriptor_GetNextDescriptor()
470 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptorType); in Cy_DMAC_Descriptor_SetDescriptorType()
Dcy_dma.c123 descriptor->ctl = in Cy_DMA_Descriptor_Init()
227 descriptor->ctl = 0UL; in Cy_DMA_Descriptor_DeInit()
338 …tor_type_t transferType = (cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl); in Cy_DMA_Descriptor_SetNextDescriptor()
385 …tor_type_t transferType = (cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl); in Cy_DMA_Descriptor_GetNextDescriptor()
446 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType); in Cy_DMA_Descriptor_SetDescriptorType()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_dma_dw.c691 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dw_connect_digital()
692 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, obj->descriptor_config.dw.triggerInType); in _cyhal_dma_dw_connect_digital()
715 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dw_enable_output()
716 obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_convert_output_t(output)); in _cyhal_dma_dw_enable_output()
737 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dw_disconnect_digital()
738 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, _cyhal_dma_dw_default_descriptor_config.… in _cyhal_dma_dw_disconnect_digital()
762 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dw_disable_output()
763 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_dma_dw_default_descriptor_config… in _cyhal_dma_dw_disable_output()
Dcyhal_dma_dmac.c982 obj->descriptor.dmac.ctl &= ~_CYHAL_DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dmac_connect_digital()
983 …obj->descriptor.dmac.ctl |= _VAL2FLD(_CYHAL_DMAC_CH_DESCR_CTL_TR_IN_TYPE, obj->descriptor_config.d… in _cyhal_dma_dmac_connect_digital()
1004 obj->descriptor.dmac.ctl &= ~_CYHAL_DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dmac_enable_output()
1005 …obj->descriptor.dmac.ctl |= _VAL2FLD(_CYHAL_DMAC_CH_DESCR_CTL_TR_OUT_TYPE, _cyhal_convert_output_t… in _cyhal_dma_dmac_enable_output()
1029 obj->descriptor.dmac.ctl &= ~_CYHAL_DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dmac_disconnect_digital()
1030 …obj->descriptor.dmac.ctl |= _VAL2FLD(_CYHAL_DMAC_CH_DESCR_CTL_TR_IN_TYPE, _cyhal_dma_dmac_default_… in _cyhal_dma_dmac_disconnect_digital()
1052 obj->descriptor.dmac.ctl &= ~_CYHAL_DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dmac_disable_output()
1053 …obj->descriptor.dmac.ctl |= _VAL2FLD(_CYHAL_DMAC_CH_DESCR_CTL_TR_OUT_TYPE, _cyhal_dma_dmac_default… in _cyhal_dma_dmac_disable_output()
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_usbd.c461 depctl_data_t ctl; in XMC_USBD_lStartWriteXfer() local
464 ctl.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; in XMC_USBD_lStartWriteXfer()
507 ctl.b.epena = 1U; in XMC_USBD_lStartWriteXfer()
508 ctl.b.cnak = 1U; in XMC_USBD_lStartWriteXfer()
509 xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = ctl.d32; in XMC_USBD_lStartWriteXfer()