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Searched refs:TRIG_OUT_MUX_1_TCPWM0_TR_IN7 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcyw20829B0_config.h402 TRIG_OUT_MUX_1_TCPWM0_TR_IN7 = 0x40000107u, /* tcpwm[0].tr_all_cnt_in[7] */ enumerator
Dcyw20829_config.h402 TRIG_OUT_MUX_1_TCPWM0_TR_IN7 = 0x40000107u, /* tcpwm[0].tr_all_cnt_in[7] */ enumerator