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Searched refs:SW_RST_R (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_sdhc.h70 __IOM uint8_t SW_RST_R; /*!< 0x0000002F Software Reset Register */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_sdhc.h70 __IOM uint8_t SW_RST_R; /*!< 0x0000002F Software Reset Register */ member
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_sdhc.c1279 while ((sdxx->base->CORE.SW_RST_R != 0) && (timeout_us-- != 0)) in _cyhal_sdxx_reset()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h1064 #define SDHC_CORE_SW_RST_R(base) (((SDHC_V1_Type *)(base))->CORE.SW_RST_R)
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h920 #define SDHC_CORE_SW_RST_R(base) (((SDHC_Type *)(base))->CORE.SW_RST_R)
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h138 #define SDHC_CORE_SW_RST_R(base) (((SDHC_Type *)(base))->CORE.SW_RST_R)