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Searched refs:SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_srss.h451 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_srss_v3_2.h956 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL macro
Dcyip_srss_v3_3.h1037 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_srss.h1180 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h249 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Pos macro
748 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_OUTPUT_DIV_Pos macro