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Searched refs:PR_LFSR_CTL0 (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_crypto.h59 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ member
Dcyip_crypto_v2.h56 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_crypto_v2.h56 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ member
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_hw.h482 #define REG_CRYPTO_PR_LFSR_CTL0(base) (((CRYPTO_Type*)(base))->PR_LFSR_CTL0)