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Searched refs:CY_ASSERT_L1 (Results 1 – 25 of 60) sorted by relevance

123

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk_v2.c72 CY_ASSERT_L1(instNum < PERI_INSTANCE_COUNT); in Cy_SysClk_PeriPclkSetDivider()
73 CY_ASSERT_L1(grpNum < PERI_PCLK_GR_NUM(instNum)); in Cy_SysClk_PeriPclkSetDivider()
114 CY_ASSERT_L1(instNum < PERI_INSTANCE_COUNT); in Cy_SysClk_PeriPclkGetDivider()
115 CY_ASSERT_L1(grpNum < PERI_PCLK_GR_NUM(instNum)); in Cy_SysClk_PeriPclkGetDivider()
121 CY_ASSERT_L1(dividerType <= CY_SYSCLK_DIV_16_BIT); in Cy_SysClk_PeriPclkGetDivider()
124 CY_ASSERT_L1(dividerNum < PERI_PCLK_GR_DIV_8_NR(instNum, grpNum)); in Cy_SysClk_PeriPclkGetDivider()
129 CY_ASSERT_L1(dividerNum < PERI_PCLK_GR_DIV_16_NR(instNum, grpNum)); in Cy_SysClk_PeriPclkGetDivider()
147 CY_ASSERT_L1(instNum < PERI_INSTANCE_COUNT); in Cy_SysClk_PeriPclkSetFracDivider()
148 CY_ASSERT_L1(grpNum < PERI_PCLK_GR_NUM(instNum)); in Cy_SysClk_PeriPclkSetFracDivider()
196 CY_ASSERT_L1(instNum < PERI_INSTANCE_COUNT); in Cy_SysClk_PeriPclkGetFracDivider()
[all …]
Dcy_prot.c130 CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); in Cy_Prot_ConfigBusMaster()
195 CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); in Cy_Prot_SetActivePC()
232 CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); in Cy_Prot_GetActivePC()
278 CY_ASSERT_L1(NULL != base); in Cy_Prot_ConfigMpuStruct()
325 CY_ASSERT_L1(NULL != base); in Cy_Prot_EnableMpuStruct()
363 CY_ASSERT_L1(NULL != base); in Cy_Prot_DisableMpuStruct()
414 CY_ASSERT_L1(NULL != base); in Cy_Prot_ConfigSmpuMasterStruct()
486 CY_ASSERT_L1(NULL != base); in Cy_Prot_ConfigSmpuSlaveStruct()
547 CY_ASSERT_L1(NULL != base); in Cy_Prot_EnableSmpuMasterStruct()
587 CY_ASSERT_L1(NULL != base); in Cy_Prot_DisableSmpuMasterStruct()
[all …]
Dcy_ipc_pipe.c98 CY_ASSERT_L1(NULL != config); in Cy_IPC_Pipe_Init()
104 CY_ASSERT_L1(NULL != config->endpointsCallbacksArray); in Cy_IPC_Pipe_Init()
105 CY_ASSERT_L1(NULL != config->userPipeIsrHandler); in Cy_IPC_Pipe_Init()
300 CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray); in Cy_IPC_Pipe_EndpointInit()
383 CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray); in Cy_IPC_Pipe_EndpointInitExt()
467 CY_ASSERT_L1(NULL != msgPtr); in Cy_IPC_Pipe_SendMessage()
468 CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray); in Cy_IPC_Pipe_SendMessage()
570 CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray); in Cy_IPC_Pipe_RegisterCallback()
574 CY_ASSERT_L1(NULL != thisEp->callbackArray); in Cy_IPC_Pipe_RegisterCallback()
620 CY_ASSERT_L1(NULL != cy_ipc_pipe_epArray); in Cy_IPC_Pipe_RegisterCallbackRel()
[all …]
Dcy_sysclk.c75 CY_ASSERT_L1(dividerType <= CY_SYSCLK_DIV_16_BIT); in Cy_SysClk_PeriphGetDivider()
79 CY_ASSERT_L1(dividerNum < PERI_DIV_8_NR); in Cy_SysClk_PeriphGetDivider()
84 CY_ASSERT_L1(dividerNum < PERI_DIV_16_NR); in Cy_SysClk_PeriphGetDivider()
128 …CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_16_5_BIT) || (dividerType == CY_SYSCLK_DIV_24_5_BIT)) … in Cy_SysClk_PeriphGetFracDivider()
133 CY_ASSERT_L1(dividerNum < PERI_DIV_16_5_NR); in Cy_SysClk_PeriphGetFracDivider()
139 CY_ASSERT_L1(dividerNum < PERI_DIV_24_5_NR); in Cy_SysClk_PeriphGetFracDivider()
169 CY_ASSERT_L1(CY_PERI_CLOCK_NR > (uint32_t)ipBlock); in Cy_SysClk_PeriphGetAssignedDivider()
256 CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || \ in Cy_SysClk_PeriphGetDividerEnabled()
323 CY_ASSERT_L1(false); in Cy_SysClk_ClkPumpSetSource()
347 CY_ASSERT_L1(false); in Cy_SysClk_ClkPumpSetDivider()
[all …]
Dcy_evtgen.c85 CY_ASSERT_L1(CY_EVTGEN_IS_DIVIDER_VALID_RANGE(refDiv)); in Cy_EvtGen_Init()
131 CY_ASSERT_L1(base); in Cy_EvtGen_DeInit()
225 CY_ASSERT_L1(CY_EVTGEN_IS_BASE_VALID(base)); in Cy_EvtGen_DeinitStruct()
226 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNum)); in Cy_EvtGen_DeinitStruct()
251 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNum)); in Cy_EvtGen_UpdateActiveCompValue()
282 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNum)); in Cy_EvtGen_UpdateDeepSleepCompValue()
Dcy_systick_v2.c49 CY_ASSERT_L1(CY_SYSTICK_IS_RELOAD_VALID(value)); in Cy_SysTick_SetReload()
76 CY_ASSERT_L1(CY_SYSTICK_IS_RELOAD_VALID(interval)); in Cy_SysTick_Init()
77 CY_ASSERT_L1(CY_SYSTICK_IS_CLK_SRC_VALID(clockSource)); in Cy_SysTick_Init()
135 CY_ASSERT_L1(CY_SYSTICK_IS_CLK_SRC_VALID(clockSource)); in Cy_SysTick_SetClockSource()
Dcy_syspm.c1905 CY_ASSERT_L1(NULL != regs); in Cy_SysPm_SaveRegisters()
1930 CY_ASSERT_L1(NULL != regs); in Cy_SysPm_RestoreRegisters()
2079 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT ); in Cy_SysPm_SetSRAMMacroPwrMode()
2092 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_SetSRAMMacroPwrMode()
2102 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
2103 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_SetSRAMMacroPwrMode()
2111 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
2112 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_SetSRAMMacroPwrMode()
2130 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT ); in Cy_SysPm_GetSRAMMacroPwrMode()
2134 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_GetSRAMMacroPwrMode()
[all …]
Dcy_crypto_core_vu.c72 CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, dstReg)); in Cy_Crypto_Core_Vu_SetMemValue()
73 …CY_ASSERT_L1( ((destAddr + byteSize) - 1u) < ((uint32_t)Cy_Crypto_Core_GetVuMemoryAddress(base) + … in Cy_Crypto_Core_Vu_SetMemValue()
104 CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, srcReg)); in Cy_Crypto_Core_Vu_GetMemValue()
105 …CY_ASSERT_L1( ((dataAddr + byteSize) - 1u) < ((uint32_t)Cy_Crypto_Core_GetVuMemoryAddress(base) + … in Cy_Crypto_Core_Vu_GetMemValue()
Dcy_crypto_core_crc_v1.c210 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcInit()
262 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcStart()
338 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_CalcFinish()
387 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V1_Crc_Calc()
Dcy_crypto_core_crc_v2.c208 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcInit()
259 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcStart()
334 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_CalcFinish()
387 CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); in Cy_Crypto_Core_V2_Crc_Calc()
Dcy_dma.c225 CY_ASSERT_L1(descriptor); in Cy_DMA_Descriptor_DeInit()
304 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); in Cy_DMA_Channel_DeInit()
337 CY_ASSERT_L1(descriptor); in Cy_DMA_Descriptor_SetNextDescriptor()
384 CY_ASSERT_L1(descriptor); in Cy_DMA_Descriptor_GetNextDescriptor()
437 CY_ASSERT_L1(descriptor); in Cy_DMA_Descriptor_SetDescriptorType()
Dcy_syspm_v3.c1498 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT ); in Cy_SysPm_SetSRAMMacroPwrMode()
1502 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_SetSRAMMacroPwrMode()
1512 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
1513 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_SetSRAMMacroPwrMode()
1521 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
1522 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_SetSRAMMacroPwrMode()
1541 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT ); in Cy_SysPm_GetSRAMMacroPwrMode()
1545 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_GetSRAMMacroPwrMode()
1553 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_GetSRAMMacroPwrMode()
1558 CY_ASSERT_L1( sramMacroNum == 0UL ); in Cy_SysPm_GetSRAMMacroPwrMode()
[all …]
Dcy_ipc_drv.c170 CY_ASSERT_L1(NULL != message); in Cy_IPC_Drv_ReadMsgWord()
225 CY_ASSERT_L1(NULL != message); in Cy_IPC_Drv_SendMsgDWord()
277 CY_ASSERT_L1(NULL != message); in Cy_IPC_Drv_ReadMsgDWord()
Dcy_ctdac.c85 CY_ASSERT_L1(NULL != base); in Cy_CTDAC_Init()
86 CY_ASSERT_L1(NULL != config); in Cy_CTDAC_Init()
210 CY_ASSERT_L1(NULL != base); in Cy_CTDAC_DeInit()
299 CY_ASSERT_L1(NULL != base); in Cy_CTDAC_FastInit()
300 CY_ASSERT_L1(NULL != config); in Cy_CTDAC_FastInit()
Dcy_axidmac.c163 CY_ASSERT_L1(CY_AXIDMAC_IS_CH_NR_VALID(channel)); in Cy_AXIDMAC_Channel_DeInit()
183 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetXloopDataCount()
204 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetXloopDataCount()
227 CY_ASSERT_L1(NULL != descriptor); in Cy_AXIDMAC_Descriptor_SetNextDescriptor()
Dcy_scb_uart.c670 CY_ASSERT_L1(NULL != context); in Cy_SCB_UART_StartRingBuffer()
672 CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); in Cy_SCB_UART_StartRingBuffer()
674 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); in Cy_SCB_UART_StartRingBuffer()
853 CY_ASSERT_L1(NULL != context); in Cy_SCB_UART_Receive()
855 CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); in Cy_SCB_UART_Receive()
857 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); in Cy_SCB_UART_Receive()
1113 CY_ASSERT_L1(NULL != context); in Cy_SCB_UART_Transmit()
1115 CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); in Cy_SCB_UART_Transmit()
1117 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); in Cy_SCB_UART_Transmit()
Dcy_sysanalog.c100 CY_ASSERT_L1(NULL != config); in Cy_SysAnalog_Init()
145 CY_ASSERT_L1(NULL != base); in Cy_SysAnalog_DeepSleepInit()
146 CY_ASSERT_L1(NULL != config); in Cy_SysAnalog_DeepSleepInit()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_evtgen.h375 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_SetStructInterrupt()
395 CY_ASSERT_L1(CY_EVTGEN_IS_MASK_VALID(mask)); in Cy_EvtGen_ClearInterrupt()
418 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_ClearStructInterrupt()
441 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_SetStructInterruptMask()
465 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_GetStructInterrupt()
489 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_GetStructInterruptMasked()
510 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_SetStructInterruptDeepSleep()
530 CY_ASSERT_L1(CY_EVTGEN_IS_MASK_VALID(mask)); in Cy_EvtGen_ClearInterruptDeepSleep()
553 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_ClearStructInterruptDeepSleep()
576 CY_ASSERT_L1(CY_EVTGEN_IS_STRUCTNUM_VALID(structNumber)); in Cy_EvtGen_SetStructInterruptDeepSleepMask()
[all …]
Dcy_axidmac.h1242 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetXloopSrcIncrement()
1267 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetXloopSrcIncrement()
1293 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetXloopDstIncrement()
1319 CY_ASSERT_L1(CY_AXIDMAC_1D_MEMORY_COPY != Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetXloopDstIncrement()
1344 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetYloopDataCount()
1370 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetYloopDataCount()
1396 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetYloopSrcIncrement()
1421 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetYloopSrcIncrement()
1447 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_SetYloopDstIncrement()
1473 CY_ASSERT_L1(CY_AXIDMAC_3D_MEMORY_COPY == Cy_AXIDMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_AXIDMAC_Descriptor_GetYloopDstIncrement()
[all …]
Dcy_dmac.h699 CY_ASSERT_L1(CY_DMAC_SCATTER_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_SetDstAddress()
723 CY_ASSERT_L1(CY_DMAC_SCATTER_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_GetDstAddress()
1140 CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_SetXloopSrcIncrement()
1166 CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_GetXloopSrcIncrement()
1191 CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_SetXloopDstIncrement()
1217 CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_GetXloopDstIncrement()
1242 CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_SetYloopDataCount()
1268 CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_GetYloopDataCount()
1293 CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_SetYloopSrcIncrement()
1319 CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); in Cy_DMAC_Descriptor_GetYloopSrcIncrement()
[all …]
Dcy_dma.h1295 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_SetXloopDataCount()
1321 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_GetXloopDataCount()
1346 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_SetXloopSrcIncrement()
1372 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_GetXloopSrcIncrement()
1397 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_SetXloopDstIncrement()
1423 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_GetXloopDstIncrement()
1448 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_SetYloopDataCount()
1474 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_GetYloopDataCount()
1499 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_SetYloopSrcIncrement()
1525 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); in Cy_DMA_Descriptor_GetYloopSrcIncrement()
[all …]
Dcy_ipc_drv.h666 CY_ASSERT_L1(CY_IPC_CHANNELS > ipcIndex); in Cy_IPC_Drv_GetIpcBaseAddress()
695 CY_ASSERT_L1(CY_IPC_INTERRUPTS > ipcIntrIndex); in Cy_IPC_Drv_GetIntrBaseAddr()
728 CY_ASSERT_L1(0UL == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); in Cy_IPC_Drv_SetInterruptMask()
729 CY_ASSERT_L1(0UL == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); in Cy_IPC_Drv_SetInterruptMask()
858 CY_ASSERT_L1(0UL == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); in Cy_IPC_Drv_SetInterrupt()
859 CY_ASSERT_L1(0UL == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); in Cy_IPC_Drv_SetInterrupt()
892 CY_ASSERT_L1(0UL == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); in Cy_IPC_Drv_ClearInterrupt()
893 CY_ASSERT_L1(0UL == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); in Cy_IPC_Drv_ClearInterrupt()
929 CY_ASSERT_L1(0UL == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); in Cy_IPC_Drv_AcquireNotify()
957 CY_ASSERT_L1(0UL == (notifyEventIntr & ~(uint32_t)(IPC_INTR_STRUCT_INTR_RELEASE_Msk))); in Cy_IPC_Drv_ReleaseNotify()
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Dcy_sar2.h919 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_Enable()
942 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_Disable()
962 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_SoftwareTrigger()
1057 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_SetInterruptMask()
1112 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_ClearInterrupt()
1138 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_GetInterruptStatus()
1162 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_GetInterruptStatusMasked()
1193 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_SetInterrupt()
1216 CY_ASSERT_L1(CY_SAR2_CHAN_NUM_VALID(base, channel)); in Cy_SAR2_Channel_GetGroupStatus()
Dcy_sar.h2452 CY_ASSERT_L1(!CY_PASS_V1); /* Deep Sleep Clock is not supported */ in Cy_SAR_SelectClock()
2481 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_FifoRead()
2507 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_FifoGetDataCount()
2543 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_ClearFifoInterrupt()
2576 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_SetFifoInterrupt()
2607 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_SetFifoInterruptMask()
2633 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_GetFifoInterruptStatus()
2662 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_GetFifoInterruptMask()
2691 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_GetFifoInterruptStatusMasked()
2719 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */ in Cy_SAR_FifoSetLevel()
[all …]
Dcy_usbfs_dev_drv.h1751 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_RegisterEndpointCallback()
2123 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_OverwriteMemcpy()
2213 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_LoadInEndpoint()
2214 …CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_DIR_IN(context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].addr… in Cy_USBFS_Dev_Drv_LoadInEndpoint()
2262 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_ReadOutEndpoint()
2263 …CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_DIR_OUT(context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].add… in Cy_USBFS_Dev_Drv_ReadOutEndpoint()
2287 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_GetEndpointAckState()
2318 CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); in Cy_USBFS_Dev_Drv_GetEndpointCount()

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