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Searched refs:CPUSS_CM7_1_DCACHE_SIZE (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h2150 #define CPUSS_CM7_1_DCACHE_SIZE 16u macro
Dtviic2d6m_config.h2297 #define CPUSS_CM7_1_DCACHE_SIZE 16u macro
Dxmc7200_config.h2735 #define CPUSS_CM7_1_DCACHE_SIZE 16u macro