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Searched refs:CFG (Results 1 – 19 of 19) sorted by relevance

/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_fce.h382 engine->kernel_ptr->CFG |= (uint32_t)event; in XMC_FCE_EnableEvent()
398 engine->kernel_ptr->CFG &= ~(uint32_t)event; in XMC_FCE_DisableEvent()
453 engine->kernel_ptr->CFG |= operation; in XMC_FCE_EnableOperation()
474 engine->kernel_ptr->CFG &= ~(uint32_t)operation; in XMC_FCE_DisableOperation()
494 engine->kernel_ptr->CFG |= (uint32_t)algo; in XMC_FCE_EnableCRCAlgorithm()
514 engine->kernel_ptr->CFG &= ~(uint32_t)algo; in XMC_FCE_DisableCRCAlgorithm()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c133 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG),
255 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
375 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
495 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
616 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
737 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
864 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
984 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_Type, CFG),
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h567 #define GPIO_PRT_CFG(base) (((GPIO_PRT_Type*)(base))->CFG)
2661 #define MCPASS_AC_CFG(base) (((MCPASS_Type *)(base))->ACTRLR.CFG)
2678 #define MCPASS_MMIO_FIFO_CFG(base) (((MCPASS_Type *)(base))->MMIO.FIFO.CFG)
2686 #define MCPASS_SAR_CTRL(base) (((MCPASS_Type *)(base))->SAR.CFG.CTRL)
2687 #define MCPASS_SAR_RESULT_INTR(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_I…
2688 #define MCPASS_SAR_RESULT_INTR_SET(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_I…
2689 #define MCPASS_SAR_RESULT_INTR_MASK(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_I…
2690 #define MCPASS_SAR_RESULT_INTR_MASKED(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_I…
2691 #define MCPASS_SAR_LIMIT_INTR(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_IN…
2692 #define MCPASS_SAR_LIMIT_INTR_SET(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_IN…
[all …]
/hal_infineon-latest/mtb-template-cat1/files/cat1b/
Dcybsp_smif_init.c56 SMIF_CFG = ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG; in cybsp_smif_disable()
60 ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG = 0x600006; in cybsp_smif_disable()
83 ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG = SMIF_CFG; in cybsp_smif_enable()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_ramc_v2.h43 …__IOM uint32_t CFG; /*!< 0x00000000 Config register with error response,… member
Dcyip_promc.h43 …__IOM uint32_t CFG; /*!< 0x00000000 Config register with error response,… member
Dcyip_ramc.h43 …__IOM uint32_t CFG; /*!< 0x00000000 Config register with error response,… member
Dcyip_gpio.h54 __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */ member
Dcyip_smif_v3.h102 …__IOM uint32_t CFG; /*!< 0x00000000 Config register with error response,… member
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_fce.c80 engine->kernel_ptr->CFG = engine->fce_cfg_update.regval; in XMC_FCE_Init()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_gpio_v3.h54 __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */ member
Dcyip_gpio_v5.h54 __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_gpio.h53 __IOM uint32_t CFG; /*!< 0x00000028 Port configuration register */ member
Dcyip_gpio_v2.h54 __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */ member
Dcyip_gpio_v5.h54 __IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1284 …e SMIF_CLK_DRIVEMODE(base) (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[1].CFG)
1285 …e SMIF_RWDS_DRIVEMODE(base) (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[2].CFG)
1989 #define GPIO_PRT_CFG(base) (((GPIO_PRT_Type*)(base))->CFG)
/hal_infineon-latest/XMCLib/devices/XMC4500/Include/
DXMC4500.h776 …__IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register … member
/hal_infineon-latest/XMCLib/devices/XMC4700/Include/
DXMC4700.h791 …__IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register … member
/hal_infineon-latest/XMCLib/devices/XMC4800/Include/
DXMC4800.h798 …__IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register … member