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/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/third_party/ethernet/include/
Dcedi.h1487 uint32_t (*setEventEnable)(void* pD, uint32_t events, uint8_t enable, uint8_t queueNum);
1548 void (*setJumboFramesRx)(void* pD, uint8_t enable);
1557 uint32_t (*getJumboFramesRx)(void* pD, uint8_t* enable);
1584 void (*setUniDirEnable)(void* pD, uint8_t enable);
1593 uint32_t (*getUniDirEnable)(void* pD, uint8_t* enable);
1603 uint32_t (*setTxChecksumOffload)(void* pD, uint8_t enable);
1613 uint32_t (*getTxChecksumOffload)(void* pD, uint8_t* enable);
1639 void (*set1536ByteFramesRx)(void* pD, uint8_t enable);
1648 uint32_t (*get1536ByteFramesRx)(void* pD, uint8_t* enable);
1656 void (*setRxChecksumOffload)(void* pD, uint8_t enable);
[all …]
Dedd_int.h236 uint32_t emacSetEventEnable(void *pD, uint32_t events, uint8_t enable,
240 uint32_t emacGetJumboFramesRx(void *pD, uint8_t *enable);
242 uint32_t emacGet1536ByteFramesRx(void *pD, uint8_t *enable);
249 uint32_t emacSetAutoNegEnable(void *pD, uint8_t enable);
296 uint32_t emacSetTxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable);
298 uint32_t emacGetTxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable);
306 uint8_t *enable, uint32_t *idleSlope);
309 uint32_t emacSetIpgStretch(void *pD, uint8_t enable, uint8_t multiplier,
353 uint32_t emacSetHdrDataSplit(void *pD, uint8_t enable);
355 uint32_t emacGetHdrDataSplit(void *pD, uint8_t *enable);
[all …]
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/third_party/ethernet/src/
Dedd.c2099 uint32_t emacSetEventEnable(void *pD, uint32_t events, uint8_t enable, in emacSetEventEnable() argument
2119 if (enable>1) { in emacSetEventEnable()
2121 "*** Error: Invalid parameter, enable: %u\n", enable); in emacSetEventEnable()
2137 if (enable) { in emacSetEventEnable()
2679 void emacSetJumboFramesRx(void *pD, uint8_t enable) in emacSetJumboFramesRx() argument
2683 if (enable>1) return; in emacSetJumboFramesRx()
2685 if (enable) in emacSetJumboFramesRx()
2692 uint32_t emacGetJumboFramesRx(void *pD, uint8_t *enable) in emacGetJumboFramesRx() argument
2694 if ((pD==NULL)||(enable==NULL)) in emacGetJumboFramesRx()
2697 *enable=EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ( in emacGetJumboFramesRx()
[all …]
Dedd_rx.c839 uint32_t emacSetHdrDataSplit(void *pD, uint8_t enable) { in emacSetHdrDataSplit() argument
842 if ((pD==NULL) || (enable>1)) in emacSetHdrDataSplit()
848 if (enable) in emacSetHdrDataSplit()
860 uint32_t emacGetHdrDataSplit(void *pD, uint8_t *enable) { in emacGetHdrDataSplit() argument
862 if ((pD==NULL) || (enable==NULL)) in emacGetHdrDataSplit()
867 *enable = EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ( in emacGetHdrDataSplit()
878 uint32_t emacSetRscEnable(void *pD, uint8_t queue, uint8_t enable) { in emacSetRscEnable() argument
885 if ((queue<1) || (queue>=(CEDI_PdVar(cfg)).rxQs) || (enable>1)) in emacSetRscEnable()
891 if (enable) in emacSetRscEnable()
905 uint32_t emacGetRscEnable(void *pD, uint8_t queue, uint8_t *enable) { in emacGetRscEnable() argument
[all …]
Dedd_tx.c961 uint32_t emacSetTxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable) in emacSetTxPartialStFwd() argument
967 if (enable>1) return EINVAL; in emacSetTxPartialStFwd()
969 if ((enable==1) && in emacSetTxPartialStFwd()
974 if (enable) { in emacSetTxPartialStFwd()
987 uint32_t emacGetTxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable) in emacGetTxPartialStFwd() argument
990 if ((pD==0)||(enable==0)||(watermark==0)) in emacGetTxPartialStFwd()
996 (*enable) = EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__READ(reg); in emacGetTxPartialStFwd()
997 if (*enable) in emacGetTxPartialStFwd()
1093 uint8_t *enable, uint32_t *idleSlope) in emacGetCbsQSetting() argument
1097 if ((pD==0)||(enable==0)||(idleSlope==0)) in emacGetCbsQSetting()
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/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_wdt_b.c276 void Cy_WDT_SetAutoService(cy_en_wdt_enable_t enable) in Cy_WDT_SetAutoService() argument
278 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_AUTO_SERVICE, enable); in Cy_WDT_SetAutoService()
294 void Cy_WDT_SetDeepSleepPause(cy_en_wdt_enable_t enable) in Cy_WDT_SetDeepSleepPause() argument
296 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_DPSLP_PAUSE, enable); in Cy_WDT_SetDeepSleepPause()
312 void Cy_WDT_SetHibernatePause(cy_en_wdt_enable_t enable) in Cy_WDT_SetHibernatePause() argument
314 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_HIB_PAUSE, enable); in Cy_WDT_SetHibernatePause()
330 void Cy_WDT_SetDebugRun(cy_en_wdt_enable_t enable) in Cy_WDT_SetDebugRun() argument
332 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_DEBUG_RUN, enable); in Cy_WDT_SetDebugRun()
Dcy_mcwdt_b.c524 void Cy_MCWDT_SetAutoService(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable) in Cy_MCWDT_SetAutoService() argument
529 … _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_AUTO_SERVICE, enable); in Cy_MCWDT_SetAutoService()
532 … _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_AUTO_SERVICE, enable); in Cy_MCWDT_SetAutoService()
607 void Cy_MCWDT_SetSleepDeepPause(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable) in Cy_MCWDT_SetSleepDeepPause() argument
612 …LR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, enable); in Cy_MCWDT_SetSleepDeepPause()
615 …LR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, enable); in Cy_MCWDT_SetSleepDeepPause()
618 …CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE, enable); in Cy_MCWDT_SetSleepDeepPause()
692 void Cy_MCWDT_SetDebugRun(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable) in Cy_MCWDT_SetDebugRun() argument
697 …) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_DEBUG_RUN, enable); in Cy_MCWDT_SetDebugRun()
700 …) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_DEBUG_RUN, enable); in Cy_MCWDT_SetDebugRun()
[all …]
Dcy_syspm_btss.c45 cy_en_btss_status_t Cy_BTSS_PowerDep(bool enable) in Cy_BTSS_PowerDep() argument
51 if(enable) in Cy_BTSS_PowerDep()
105 cy_en_btss_status_t Cy_BTSS_CPUSSPowerDep(bool enable) in Cy_BTSS_CPUSSPowerDep() argument
112 if(enable) in Cy_BTSS_CPUSSPowerDep()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_tcpwm_shiftreg.h238 …C_INLINE void Cy_TCPWM_ShiftReg_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
243 …C_INLINE void Cy_TCPWM_ShiftReg_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
251 __STATIC_INLINE void Cy_TCPWM_Shiftreg_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
527 …C_INLINE void Cy_TCPWM_ShiftReg_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_ShiftReg_EnableCompare0Swap() argument
529 Cy_TCPWM_Block_EnableCompare0Swap(base, cntNum, enable); in Cy_TCPWM_ShiftReg_EnableCompare0Swap()
550 …C_INLINE void Cy_TCPWM_ShiftReg_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_ShiftReg_EnableCompare1Swap() argument
552 Cy_TCPWM_Block_EnableCompare1Swap(base, cntNum, enable); in Cy_TCPWM_ShiftReg_EnableCompare1Swap()
718 __STATIC_INLINE void Cy_TCPWM_Shiftreg_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Shiftreg_EnableSwap() argument
720 Cy_TCPWM_Block_EnableSwap(base, cntNum, enable); in Cy_TCPWM_Shiftreg_EnableSwap()
Dcy_tcpwm_counter.h272 …IC_INLINE void Cy_TCPWM_Counter_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
284 …C_INLINE void Cy_TCPWM_Counter_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
287 __STATIC_INLINE void Cy_TCPWM_Counter_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
553 …IC_INLINE void Cy_TCPWM_Counter_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Counter_EnableCompare0Swap() argument
555 Cy_TCPWM_Block_EnableCompare0Swap(base, cntNum, enable); in Cy_TCPWM_Counter_EnableCompare0Swap()
820 …IC_INLINE void Cy_TCPWM_Counter_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Counter_EnableCompare1Swap() argument
822 Cy_TCPWM_Block_EnableCompare1Swap(base, cntNum, enable); in Cy_TCPWM_Counter_EnableCompare1Swap()
843 __STATIC_INLINE void Cy_TCPWM_Counter_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Counter_EnableSwap() argument
845 Cy_TCPWM_Block_EnableSwap(base, cntNum, enable); in Cy_TCPWM_Counter_EnableSwap()
Dcy_tcpwm_quaddec.h263 …IC_INLINE void Cy_TCPWM_QuadDec_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
273 …C_INLINE void Cy_TCPWM_QuadDec_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
281 __STATIC_INLINE void Cy_TCPWM_QuadDec_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
546 …IC_INLINE void Cy_TCPWM_QuadDec_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_QuadDec_EnableCompare0Swap() argument
548 Cy_TCPWM_Block_EnableCompare0Swap(base, cntNum, enable); in Cy_TCPWM_QuadDec_EnableCompare0Swap()
762 …IC_INLINE void Cy_TCPWM_QuadDec_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_QuadDec_EnableCompare1Swap() argument
764 Cy_TCPWM_Block_EnableCompare1Swap(base, cntNum, enable); in Cy_TCPWM_QuadDec_EnableCompare1Swap()
912 __STATIC_INLINE void Cy_TCPWM_QuadDec_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_QuadDec_EnableSwap() argument
914 Cy_TCPWM_Block_EnableSwap(base, cntNum, enable); in Cy_TCPWM_QuadDec_EnableSwap()
Dcy_tcpwm_pwm.h419 __STATIC_INLINE void Cy_TCPWM_PWM_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable…
426 __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
436 __STATIC_INLINE void Cy_TCPWM_PWM_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
745 …STATIC_INLINE void Cy_TCPWM_PWM_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_PWM_EnableCompare0Swap() argument
747 Cy_TCPWM_Block_EnableCompare0Swap(base, cntNum, enable); in Cy_TCPWM_PWM_EnableCompare0Swap()
768 …STATIC_INLINE void Cy_TCPWM_PWM_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_PWM_EnableCompare1Swap() argument
770 Cy_TCPWM_Block_EnableCompare1Swap(base, cntNum, enable); in Cy_TCPWM_PWM_EnableCompare1Swap()
958 __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_PWM_EnablePeriodSwap() argument
962 if (enable) in Cy_TCPWM_PWM_EnablePeriodSwap()
971 if (enable) in Cy_TCPWM_PWM_EnablePeriodSwap()
[all …]
Dcy_tcpwm.h571 …INLINE cy_en_tcpwm_status_t Cy_TCPWM_SetDebugFreeze (TCPWM_Type *base, uint32 cntNum, bool enable);
582 …TIC_INLINE void Cy_TCPWM_Block_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
584 …TIC_INLINE void Cy_TCPWM_Block_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable);
591 __STATIC_INLINE void Cy_TCPWM_Block_EnableSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
679 …ATIC_INLINE void Cy_TCPWM_Block_EnableCompare0Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Block_EnableCompare0Swap() argument
683 if (enable) in Cy_TCPWM_Block_EnableCompare0Swap()
692 if (enable) in Cy_TCPWM_Block_EnableCompare0Swap()
705 …ATIC_INLINE void Cy_TCPWM_Block_EnableCompare1Swap(TCPWM_Type *base, uint32_t cntNum, bool enable) in Cy_TCPWM_Block_EnableCompare1Swap() argument
709 if (enable) in Cy_TCPWM_Block_EnableCompare1Swap()
1523 …_INLINE cy_en_tcpwm_status_t Cy_TCPWM_SetDebugFreeze (TCPWM_Type *base, uint32 cntNum, bool enable) in Cy_TCPWM_SetDebugFreeze() argument
[all …]
Dcy_wdt.h528 void Cy_WDT_SetAutoService(cy_en_wdt_enable_t enable);
529 void Cy_WDT_SetDeepSleepPause(cy_en_wdt_enable_t enable);
530 void Cy_WDT_SetHibernatePause(cy_en_wdt_enable_t enable);
531 void Cy_WDT_SetDebugRun(cy_en_wdt_enable_t enable);
Dcy_mcwdt.h578 #define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable)) argument
617 …d Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
661 void Cy_MCWDT_SetAutoService(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
664 void Cy_MCWDT_SetSleepDeepPause(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
665 void Cy_MCWDT_SetDebugRun(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
1030 …E void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable) in Cy_MCWDT_SetClearOnMatch() argument
1033 CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable)); in Cy_MCWDT_SetClearOnMatch()
1037 …T_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable); in Cy_MCWDT_SetClearOnMatch()
1041 …T_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable); in Cy_MCWDT_SetClearOnMatch()
Dcy_syspm_btss.h132 cy_en_btss_status_t Cy_BTSS_PowerDep(bool enable);
149 cy_en_btss_status_t Cy_BTSS_CPUSSPowerDep(bool enable);
Dcy_syspm.h2031 #define CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS… argument
2032 enable)
2035 #define CY_SYSPM_CORE_BUCK_OVERRRIDE_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, … argument
2036 enable)
2039 #define CY_SYSPM_CORE_BUCK_COPY_SETTINGS_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CT… argument
2040 enable)
5229 void Cy_SysPm_CpuSleepOnExit(bool enable);
6799 void Cy_SysPm_BgRefCtrl(bool enable);
7348 void Cy_SysPm_CoreBuckDpslpEnableOverride(bool enable);
7474 void Cy_SysPm_SramLdoEnable(bool enable);
[all …]
/hal_infineon-3.7.0/mtb-hal-cat1/include_pvt/
Dcyhal_pwm_impl.h71 …hal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intr_priority, bool enable) in _cyhal_pwm_enable_event() argument
74 _cyhal_tcpwm_enable_event(&obj->tcpwm, &obj->tcpwm.resource, converted, intr_priority, enable); in _cyhal_pwm_enable_event()
77 #define cyhal_pwm_enable_event(obj, event, intr_priority, enable) \ argument
78 _cyhal_pwm_enable_event(obj, event, intr_priority, enable)
Dcyhal_quaddec_impl.h75 bool enable) in _cyhal_quaddec_enable_event() argument
79 enable); in _cyhal_quaddec_enable_event()
82 #define cyhal_quaddec_enable_event(obj, event, intr_priority, enable) \ argument
83 _cyhal_quaddec_enable_event(obj, event, intr_priority, enable)
Dcyhal_timer_impl.h84 …e_event_internal(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intr_priority, bool enable) in cyhal_timer_enable_event_internal() argument
87 _cyhal_tcpwm_enable_event(&obj->tcpwm, &obj->tcpwm.resource, converted, intr_priority, enable); in cyhal_timer_enable_event_internal()
90 …nable_event(obj, event, intr_priority, enable) cyhal_timer_enable_event_internal(obj, event, intr_… argument
Dcyhal_i2s_impl.h43 #define cyhal_i2s_enable_event(obj, event, intr_priority, enable) \ argument
44 …cyhal_audioss_enable_event((_cyhal_audioss_t *)(obj), (uint32_t)(event), (intr_priority), (enable))
/hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1b/COMPONENT_MTB/COMPONENT_CM33/COMPONENT_SECURE_APP/
Ds_func.c12 void __attribute__((cmse_nonsecure_entry)) secure_systick_entry(bool enable) { in secure_systick_entry() argument
13 if(enable) in secure_systick_entry()
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_comp.c195 …_comp_enable_event(cyhal_comp_t *obj, cyhal_comp_event_t event, uint8_t intr_priority, bool enable) in cyhal_comp_enable_event() argument
202 _cyhal_comp_ctb_enable_event(obj, event, intr_priority, enable); in cyhal_comp_enable_event()
208 _cyhal_comp_lp_enable_event(obj, event, intr_priority, enable); in cyhal_comp_enable_event()
/hal_infineon-3.7.0/mtb-hal-cat1/include/
Dcyhal_usb_dev.h273 void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable);
374 cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enable ,cyhal_usb_dev_e…
502 void cyhal_usb_dev_irq_enable(cyhal_usb_dev_t *obj, bool enable);
/hal_infineon-3.7.0/btstack-integration/COMPONENT_BTSS-IPC/platform/ipc/include/
Dcybt_platform_internal.h28 #define CONTROLLER_SLEEP(enable) (Cy_BTSS_PowerDep(enable)) argument

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