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Searched refs:CY_SAR_VREF_SEL_BGR (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.7.0/mtb-hal-cat1/COMPONENT_CAT1B/include/
Dcyhal_missing_pdl.h180 CY_SAR_VREF_SEL_BGR = 4UL, enumerator
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_adc_sar.c417 #define _CYHAL_ADC_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_BGR \
737 return CY_SAR_VREF_SEL_BGR; in _cyhal_adc_convert_vref()
746 return CY_SAR_VREF_SEL_BGR; in _cyhal_adc_convert_vref()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_sar.h953CY_SAR_VREF_SEL_BGR = 4UL << SAR_CTRL_VREF_SEL_Pos, /**< System wide bandgap from \ref… enumerator