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Searched refs:PCLK_TCPWM0_CLOCKS0 (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-3.6.0/mtb-hal-cat1/include_pvt/
Dcyhal_peri_common.h38 #define _CYHAL_TCPWM0_PCLK_CLOCK0 PCLK_TCPWM0_CLOCKS0
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h52 PCLK_TCPWM0_CLOCKS0 = 0x0013u, /* tcpwm[0].clocks[0] */ enumerator
Dpsoc6_04_config.h40 PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ enumerator
Dpsoc6_03_config.h42 PCLK_TCPWM0_CLOCKS0 = 0x0009u, /* tcpwm[0].clocks[0] */ enumerator
Dpsoc6_02_config.h48 PCLK_TCPWM0_CLOCKS0 = 0x000Fu, /* tcpwm[0].clocks[0] */ enumerator
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h77 PCLK_TCPWM0_CLOCKS0 = 0x0126u, /* tcpwm[0].clocks[0] */ enumerator
Dxmc7200_config.h39 PCLK_TCPWM0_CLOCKS0 = 0x0006u, /* tcpwm[0].clocks[0] */ enumerator