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Searched refs:CY_BLE_PMU_PMU_CTRL_REG (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_ble_clk.c116 #define CY_BLE_PMU_PMU_CTRL_REG (0x1e03u) macro
765 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp); in Cy_BLE_HAL_MxdRadioEnableClocks()
771 … status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_PMU_CTRL_REG, CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL); in Cy_BLE_HAL_MxdRadioEnableClocks()
774 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp); in Cy_BLE_HAL_MxdRadioEnableClocks()
/hal_infineon-3.6.0/bless/
Dcy_ble_clk.c116 #define CY_BLE_PMU_PMU_CTRL_REG (0x1e03u) macro
765 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp); in Cy_BLE_HAL_MxdRadioEnableClocks()
771 … status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_PMU_CTRL_REG, CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL); in Cy_BLE_HAL_MxdRadioEnableClocks()
774 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp); in Cy_BLE_HAL_MxdRadioEnableClocks()