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Searched refs:P3_0_TCPWM0_LINE1 (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dgpio_xmc7100_100_teqfp.h672 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ enumerator
Dgpio_xmc7100_144_teqfp.h939 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ enumerator
Dgpio_xmc7100_176_teqfp.h1140 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ enumerator
Dgpio_xmc7100_272_bga.h1490 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ enumerator
/hal_infineon-3.5.0/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/
Dcyhal_xmc7100_100_teqfp.c777 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1},
Dcyhal_xmc7100_144_teqfp.c948 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1},
Dcyhal_xmc7100_176_teqfp.c1056 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1},
Dcyhal_xmc7100_272_bga.c1169 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1},