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Searched refs:CH (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/drivers/dma/
Ddma_xmc4xxx.c202 dma->CH[channel].SAR = block->source_address; in dma_xmc4xxx_config()
203 dma->CH[channel].DAR = block->dest_address; in dma_xmc4xxx_config()
204 dma->CH[channel].LLP = 0; in dma_xmc4xxx_config()
207 dma->CH[channel].CTLH = block->block_size / config->source_data_size; in dma_xmc4xxx_config()
210 dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) | in dma_xmc4xxx_config()
213 dma->CH[channel].CTLL = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos | in dma_xmc4xxx_config()
259 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4; in dma_xmc4xxx_config()
260 dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_DST_Pos); in dma_xmc4xxx_config()
261 dma->CH[channel].CTLL |= 1 << GPDMA0_CH_CTLL_TT_FC_Pos; in dma_xmc4xxx_config()
265 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_SRC_PER_Pos) | 4; in dma_xmc4xxx_config()
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Ddma_mcux_edma.c162 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
163 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
164 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
165 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
166 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CSR)
777 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
778 LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR); in dma_mcux_edma_get_status()
779 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
780 LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT); in dma_mcux_edma_get_status()
781 LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR); in dma_mcux_edma_get_status()
/Zephyr-latest/drivers/pwm/
Dpwm_nxp_s32_emios.c282 if (config->base->CH.UC[channel].C & eMIOS_C_FEN_MASK) { in pwm_nxp_s32_capture_configure()
322 if (config->base->CH.UC[channel].C & eMIOS_C_FEN_MASK) { in pwm_nxp_s32_capture_enable()
372 bus_select = (config->base->CH.UC[channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT; in pwm_nxp_s32_get_master_bus()
423 internal_prescaler = (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCEXTPRE_MASK) >> in pwm_nxp_s32_get_cycles_per_sec()
427 if (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCPRECLK_MASK) { in pwm_nxp_s32_get_cycles_per_sec()
/Zephyr-latest/boards/st/nucleo_wb55rg/doc/
Dnucleo_wb55rg.rst218 - PWM_2 CH 1 : PA0
/Zephyr-latest/boards/adi/max78002evkit/doc/
Dindex.rst231 | JP31 | L/R SEL | Select MIC ON R/L CH, I2S microphone data stream …
/Zephyr-latest/boards/nxp/mr_canhubk3/doc/
Dindex.rst106 can_led1 Red PTE5 FXIO D7 / EMIOS1 CH5 / EMIOS0 CH 19