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Searched refs:edge (Results 1 – 13 of 13) sorted by relevance

/hal_infineon-3.4.0/XMCLib/drivers/src/
Dxmc_ccu4.c111 #define XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ argument
112 ((edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \
113 (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \
114 (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \
115 (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE))
679 XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
688 XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
699 ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS2_EV1EM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
703 ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS2_EV2EM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
739 ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS_EV1EM_Pos; in XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent()
[all …]
Dxmc_eru.c94 #define XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge) \ argument
95 ((edge == XMC_ERU_ETL_EDGE_DETECTION_DISABLED) || \
96 (edge == XMC_ERU_ETL_EDGE_DETECTION_RISING) || \
97 (edge == XMC_ERU_ETL_EDGE_DETECTION_FALLING) || \
98 (edge == XMC_ERU_ETL_EDGE_DETECTION_BOTH))
Dxmc_ccu8.c130 #define XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ argument
131 ((edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \
132 (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \
133 (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \
134 (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE))
726 XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
735 XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
747 ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS2_EV1EM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
751 ins |= ((uint32_t) ev2_config->edge) << CCU8_CC8_INS2_EV2EM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
786 ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS_EV1EM_Pos; in XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent()
[all …]
Dxmc_hrpwm.c454 reg |= ((uint32_t) config->edge) << HRPWM0_CSG_CC_BLMC_Pos; in XMC_HRPWM_CSG_SelBlankingInput()
485 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STRES_Pos; in XMC_HRPWM_CSG_StartSlopeGenConfig()
496 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STPES_Pos; in XMC_HRPWM_CSG_StopSlopeGenConfig()
507 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_TRGES_Pos; in XMC_HRPWM_CSG_TriggerDACConvConfig()
518 csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STES_Pos; in XMC_HRPWM_CSG_TriggerShadowXferConfig()
Dxmc_bccu.c129 void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge) in XMC_BCCU_SetTrapEdge() argument
132 bccu->GLOBCON |= ((uint32_t)edge << BCCU_GLOBCON_TRAPED_Pos); in XMC_BCCU_SetTrapEdge()
414 void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_… in XMC_BCCU_CH_ConfigTrigger() argument
419 reg = ((uint32_t)edge << BCCU_CH_CHCONFIG_TRED_Pos); in XMC_BCCU_CH_ConfigTrigger()
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/
Dcy_ctb.h444 #define CY_CTB_COMPEDGE(edge) (((edge) == CY_CTB_COMP_EDGE_DISABLE) \ argument
445 || ((edge) == CY_CTB_COMP_EDGE_RISING) \
446 || ((edge) == CY_CTB_COMP_EDGE_FALLING) \
447 || ((edge) == CY_CTB_COMP_EDGE_BOTH))
1067 …mpSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge);
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/source/
Dcyhal_gpio.c94 … cyhal_gpio_event_t event, edge = (cyhal_gpio_event_t)Cy_GPIO_GetInterruptEdge(portAddr, pin); in _cyhal_gpio_irq_handler() local
95 switch (edge) in _cyhal_gpio_irq_handler()
99 event = edge; in _cyhal_gpio_irq_handler()
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/
Dcy_ctb.c1468 …ompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge) in Cy_CTB_CompSetInterruptEdgeType() argument
1471 CY_ASSERT_L3(CY_CTB_COMPEDGE(edge)); in Cy_CTB_CompSetInterruptEdgeType()
1478 CTBM_OA_RES0_CTRL(base) = opampCtrlReg | (uint32_t) edge; in Cy_CTB_CompSetInterruptEdgeType()
1484 CTBM_OA_RES1_CTRL(base) = opampCtrlReg | (uint32_t) edge; in Cy_CTB_CompSetInterruptEdgeType()
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc_bccu.h622 void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge);
1336 void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_…
Dxmc_ccu4.h645 …XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input sig… member
Dxmc_hrpwm.h757 XMC_HRPWM_CSG_EDGE_SEL_t edge; /**< Active edge of mapped_input */ member
Dxmc_ccu8.h863 …XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input sig… member
/hal_infineon-3.4.0/mtb-hal-cat1/
DRELEASE.md51 …able_output updated to require a new argument to specify whether the signal is level or edge based.