1/* 2 * Copyright (c) 2024 EPAM Systems 3 * Copyright (c) 2024 Renesas Electronics Corporation 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <dt-bindings/i2c/i2c.h> 9#include <mem.h> 10#include <freq.h> 11#include <zephyr/dt-bindings/adc/adc.h> 12 13/ { 14 compatible = "renesas,r9a08g045"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-m33"; 25 reg = <0>; 26 clock-frequency = <250000000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 mpu: mpu@e000ed90 { 31 compatible = "arm,armv8m-mpu"; 32 reg = <0xe000ed90 0x40>; 33 }; 34 }; 35 }; 36 37 osc: osc { 38 compatible = "fixed-clock"; 39 clock-frequency = <DT_FREQ_M(24)>; 40 #clock-cells = <0>; 41 }; 42 43 soc { 44 cpg: clock-controller@41010000 { 45 compatible = "renesas,rz-cpg"; 46 reg = <0x41010000 0x10000>; 47 clocks = <&osc>; 48 #clock-cells = <1>; 49 status = "okay"; 50 51 iclk: iclk { 52 compatible = "fixed-clock"; 53 clock-frequency = <DT_FREQ_M(1100)>; 54 #clock-cells = <0>; 55 }; 56 57 p0clk: p0clk { 58 compatible = "fixed-clock"; 59 clock-frequency = <DT_FREQ_M(100)>; 60 #clock-cells = <0>; 61 }; 62 63 p4clk: p4clk { 64 compatible = "fixed-clock"; 65 clock-frequency = <DT_FREQ_M(160)>; 66 #clock-cells = <0>; 67 }; 68 69 p5clk: p5clk { 70 compatible = "fixed-clock"; 71 clock-frequency = <DT_FREQ_M(200)>; 72 #clock-cells = <0>; 73 }; 74 75 tsuclk: tsuclk { 76 compatible = "fixed-clock"; 77 clock-frequency = <DT_FREQ_M(100)>; 78 #clock-cells = <0>; 79 }; 80 81 sd0clk: sd0clk { 82 compatible = "fixed-clock"; 83 clock-frequency = <133333333>; 84 #clock-cells = <0>; 85 }; 86 87 sd1clk: sd1clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <133333333>; 90 #clock-cells = <0>; 91 }; 92 93 sd2clk: sd2clk { 94 compatible = "fixed-clock"; 95 clock-frequency = <133333333>; 96 #clock-cells = <0>; 97 }; 98 99 m0clk: m0clk { 100 compatible = "fixed-clock"; 101 clock-frequency = <DT_FREQ_M(200)>; 102 #clock-cells = <0>; 103 }; 104 105 p1clk: p1clk { 106 compatible = "fixed-clock"; 107 clock-frequency = <DT_FREQ_M(200)>; 108 #clock-cells = <0>; 109 }; 110 111 p2clk: p2clk { 112 compatible = "fixed-clock"; 113 clock-frequency = <DT_FREQ_M(100)>; 114 #clock-cells = <0>; 115 }; 116 117 p3clk: p3clk { 118 compatible = "fixed-clock"; 119 clock-frequency = <DT_FREQ_M(200)>; 120 #clock-cells = <0>; 121 }; 122 123 atclk: atclk { 124 compatible = "fixed-clock"; 125 clock-frequency = <DT_FREQ_M(400)>; 126 #clock-cells = <0>; 127 }; 128 129 ztclk: ztclk { 130 compatible = "fixed-clock"; 131 clock-frequency = <DT_FREQ_M(100)>; 132 #clock-cells = <0>; 133 }; 134 135 oc0clk: oc0clk { 136 compatible = "fixed-clock"; 137 clock-frequency = <33333333>; 138 #clock-cells = <0>; 139 }; 140 141 oc1clk: oc1clk { 142 compatible = "fixed-clock"; 143 clock-frequency = <16666666>; 144 #clock-cells = <0>; 145 }; 146 147 spi0clk: spi0clk { 148 compatible = "fixed-clock"; 149 clock-frequency = <33333333>; 150 #clock-cells = <0>; 151 }; 152 153 spi1clk: spi1clk { 154 compatible = "fixed-clock"; 155 clock-frequency = <16666666>; 156 #clock-cells = <0>; 157 }; 158 159 s0clk: s0clk { 160 compatible = "fixed-clock"; 161 clock-frequency = <DT_FREQ_M(400)>; 162 #clock-cells = <0>; 163 }; 164 165 i2clk: i2clk { 166 compatible = "fixed-clock"; 167 clock-frequency = <DT_FREQ_M(250)>; 168 #clock-cells = <0>; 169 }; 170 171 i3clk: i3clk { 172 compatible = "fixed-clock"; 173 clock-frequency = <DT_FREQ_M(250)>; 174 #clock-cells = <0>; 175 }; 176 177 hpclk: hpclk { 178 compatible = "fixed-clock"; 179 clock-frequency = <DT_FREQ_M(250)>; 180 #clock-cells = <0>; 181 }; 182 183 oscclk: oscclk { 184 compatible = "fixed-clock"; 185 clock-frequency = <DT_FREQ_M(24)>; 186 #clock-cells = <0>; 187 }; 188 189 osc2clk: osc2clk { 190 compatible = "fixed-clock"; 191 clock-frequency = <DT_FREQ_M(8)>; 192 #clock-cells = <0>; 193 }; 194 }; 195 196 adc: adc@40058000 { 197 compatible = "renesas,rz-adc"; 198 reg = <0x40058000 0x80>; 199 interrupts = <312 3>; 200 interrupt-names = "scanend"; 201 #io-channel-cells = <1>; 202 vref-mv = <1800>; 203 channel-available-mask = <0x01FF>; 204 status = "disabled"; 205 }; 206 207 pinctrl: pin-controller@41030000 { 208 compatible = "renesas,rzg-pinctrl"; 209 reg = <0x41030000 DT_SIZE_K(64)>; 210 reg-names = "pinctrl"; 211 212 gpio: gpio-common { 213 compatible = "renesas,rz-gpio-int"; 214 interrupts = 215 <429 10>, <430 10>, <431 10>, <432 10>, 216 <433 10>, <434 10>, <435 10>, <436 10>, 217 <437 10>, <438 10>, <439 10>, <440 10>, 218 <441 10>, <442 10>, <443 10>, <444 10>, 219 <445 10>, <446 10>, <447 10>, <448 10>, 220 <449 10>, <450 10>, <451 10>, <452 10>, 221 <453 10>, <454 10>, <455 10>, <456 10>, 222 <457 10>, <458 10>, <459 10>, <460 10>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 227 gpio0: gpio@0 { 228 compatible = "renesas,rz-gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 ngpios = <4>; 232 reg = <0x0>; 233 status = "disabled"; 234 }; 235 236 gpio1: gpio@1000 { 237 compatible = "renesas,rz-gpio"; 238 gpio-controller; 239 #gpio-cells= <2>; 240 ngpios = <5>; 241 reg = <0x1000>; 242 status = "disabled"; 243 }; 244 245 gpio2: gpio@1100 { 246 compatible = "renesas,rz-gpio"; 247 gpio-controller; 248 #gpio-cells= <2>; 249 ngpios = <4>; 250 reg = <0x1100>; 251 status = "disabled"; 252 }; 253 254 gpio3: gpio@1200 { 255 compatible = "renesas,rz-gpio"; 256 gpio-controller; 257 #gpio-cells= <2>; 258 ngpios = <4>; 259 reg = <0x1200>; 260 status = "disabled"; 261 }; 262 263 gpio4: gpio@1300 { 264 compatible = "renesas,rz-gpio"; 265 gpio-controller; 266 #gpio-cells= <2>; 267 ngpios = <6>; 268 reg = <0x1300>; 269 status = "disabled"; 270 }; 271 272 gpio5: gpio@100 { 273 compatible = "renesas,rz-gpio"; 274 gpio-controller; 275 #gpio-cells= <2>; 276 ngpios = <5>; 277 reg = <0x100>; 278 status = "disabled"; 279 }; 280 281 gpio6: gpio@200 { 282 compatible = "renesas,rz-gpio"; 283 gpio-controller; 284 #gpio-cells= <2>; 285 ngpios = <5>; 286 reg = <0x200>; 287 status = "disabled"; 288 }; 289 290 gpio7: gpio@1400 { 291 compatible = "renesas,rz-gpio"; 292 gpio-controller; 293 #gpio-cells= <2>; 294 ngpios = <5>; 295 reg = <0x1400>; 296 status = "disabled"; 297 }; 298 299 gpio8: gpio@1500 { 300 compatible = "renesas,rz-gpio"; 301 gpio-controller; 302 #gpio-cells= <2>; 303 ngpios = <5>; 304 reg = <0x1500>; 305 status = "disabled"; 306 }; 307 308 gpio9: gpio@1600 { 309 compatible = "renesas,rz-gpio"; 310 gpio-controller; 311 #gpio-cells= <2>; 312 ngpios = <4>; 313 reg = <0x1600>; 314 status = "disabled"; 315 }; 316 317 gpio10: gpio@1700 { 318 compatible = "renesas,rz-gpio"; 319 gpio-controller; 320 #gpio-cells= <2>; 321 ngpios = <5>; 322 reg = <0x1700>; 323 status = "disabled"; 324 }; 325 326 gpio11: gpio@300 { 327 compatible = "renesas,rz-gpio"; 328 gpio-controller; 329 #gpio-cells= <2>; 330 ngpios = <4>; 331 reg = <0x300>; 332 status = "disabled"; 333 }; 334 335 gpio12: gpio@400 { 336 compatible = "renesas,rz-gpio"; 337 gpio-controller; 338 #gpio-cells= <2>; 339 ngpios = <2>; 340 reg = <0x400>; 341 status = "disabled"; 342 }; 343 344 gpio13: gpio@500 { 345 compatible = "renesas,rz-gpio"; 346 gpio-controller; 347 #gpio-cells= <2>; 348 ngpios = <5>; 349 reg = <0x500>; 350 status = "disabled"; 351 }; 352 353 gpio14: gpio@600 { 354 compatible = "renesas,rz-gpio"; 355 gpio-controller; 356 #gpio-cells= <2>; 357 ngpios = <3>; 358 reg = <0x600>; 359 status = "disabled"; 360 }; 361 362 gpio15: gpio@700 { 363 compatible = "renesas,rz-gpio"; 364 gpio-controller; 365 #gpio-cells= <2>; 366 ngpios = <4>; 367 reg = <0x700>; 368 status = "disabled"; 369 }; 370 371 gpio16: gpio@800 { 372 compatible = "renesas,rz-gpio"; 373 gpio-controller; 374 #gpio-cells= <2>; 375 ngpios = <2>; 376 reg = <0x800>; 377 status = "disabled"; 378 }; 379 380 gpio17: gpio@900 { 381 compatible = "renesas,rz-gpio"; 382 gpio-controller; 383 #gpio-cells= <2>; 384 ngpios = <4>; 385 reg = <0x900>; 386 status = "disabled"; 387 }; 388 389 gpio18: gpio@A00 { 390 compatible = "renesas,rz-gpio"; 391 gpio-controller; 392 #gpio-cells=<2>; 393 ngpios = <6>; 394 reg = <0xA00>; 395 status = "disabled"; 396 }; 397 }; 398 }; 399 400 dma0: dma@41800000 { /* Secure DMA */ 401 compatible = "renesas,rz-dma"; 402 reg = <0x41800000 0x800>, <0x41810000 0x20>; 403 reg-names = "reg_main", "ext"; 404 interrupts = <95 1>, <96 1>, <97 1>, <98 1>, 405 <99 1>, <100 1>, <101 1>, <102 1>, 406 <103 1>, <104 1>, <105 1>, <106 1>, 407 <107 1>, <108 1>, <109 1>, <110 1>, 408 <94 1>; /* DMAERR1 */ 409 interrupt-names = "ch0", "ch1", "ch2", "ch3", 410 "ch4", "ch5", "ch6", "ch7", 411 "ch8", "ch9", "ch10", "ch11", 412 "ch12", "ch13", "ch14", "ch15", 413 "err1"; 414 dma-channels = <16>; 415 #dma-cells = <2>; 416 dma-buf-addr-alignment = <4>; 417 status = "disabled"; 418 }; 419 420 scif0: serial@4004b800 { 421 compatible = "renesas,rz-scif-uart"; 422 channel = <0>; 423 reg = <0x4004b800 0x18>; 424 interrupts = <320 1>, <321 1>, <322 1>, <323 1>, <324 1>; 425 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 426 status = "disabled"; 427 }; 428 scif1: serial@4004bc00 { 429 compatible = "renesas,rz-scif-uart"; 430 channel = <1>; 431 reg = <0x4004bc00 0x18>; 432 interrupts = <325 1>, <326 1>, <327 1>, <328 1>, <329 1>; 433 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 434 status = "disabled"; 435 }; 436 scif2: serial@4004c000 { 437 compatible = "renesas,rz-scif-uart"; 438 channel = <2>; 439 reg = <0x4004c000 0x18>; 440 interrupts = <330 1>, <331 1>, <332 1>, <333 1>, <334 1>; 441 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 442 status = "disabled"; 443 }; 444 scif3: serial@4004c400 { 445 compatible = "renesas,rz-scif-uart"; 446 channel = <3>; 447 reg = <0x4004c400 0x18>; 448 interrupts = <335 1>, <336 1>, <337 1>, <338 1>, <339 1>; 449 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 450 status = "disabled"; 451 }; 452 scif4: serial@4004c800 { 453 compatible = "renesas,rz-scif-uart"; 454 channel = <4>; 455 reg = <0x4004c800 0x18>; 456 interrupts = <340 1>, <341 1>, <342 1>, <343 1>, <344 1>; 457 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 458 status = "disabled"; 459 }; 460 scif5: serial@4004e000 { 461 compatible = "renesas,rz-scif-uart"; 462 channel = <5>; 463 reg = <0x4004e000 0x18>; 464 interrupts = <345 1>, <346 1>, <347 1>, <348 1>, <349 1>; 465 interrupt-names = "eri", "bri", "rxi", "txi", "tei"; 466 status = "disabled"; 467 }; 468 469 i2c0: i2c@40090000 { 470 compatible = "renesas,rz-riic"; 471 channel = <0>; 472 clock-frequency = <I2C_BITRATE_STANDARD>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <0x40090000 0x15>; 476 interrupts = <257 1>, <258 1>, <259 1>, <260 1>, 477 <261 1>, <262 1>, <263 1>, <264 1>; 478 interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi"; 479 status = "disabled"; 480 }; 481 i2c1: i2c@40090400 { 482 compatible = "renesas,rz-riic"; 483 channel = <1>; 484 clock-frequency = <I2C_BITRATE_STANDARD>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x40090400 0x15>; 488 interrupts = <265 1>, <266 1>, <267 1>, <268 1>, 489 <269 1>, <270 1>, <271 1>, <272 1>; 490 interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi"; 491 status = "disabled"; 492 }; 493 i2c2: i2c@40090800 { 494 compatible = "renesas,rz-riic"; 495 channel = <2>; 496 clock-frequency = <I2C_BITRATE_STANDARD>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <0x40090800 0x15>; 500 interrupts = <273 1>, <274 1>, <275 1>, <276 1>, 501 <277 1>, <278 1>, <279 1>, <280 1>; 502 interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi"; 503 status = "disabled"; 504 }; 505 i2c3: i2c@40090c00 { 506 compatible = "renesas,rz-riic"; 507 channel = <3>; 508 clock-frequency = <I2C_BITRATE_STANDARD>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0x40090c00 0x15>; 512 interrupts = <281 1>, <282 1>, <283 1>, <284 1>, 513 <285 1>, <286 1>, <287 1>, <288 1>; 514 interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi"; 515 status = "disabled"; 516 }; 517 518 gtm0: gtm@42801000 { 519 compatible = "renesas,rz-gtm"; 520 reg = <0x42801000 0x30>; 521 channel = <0>; 522 interrupts = <44 1>; 523 interrupt-names = "overflow"; 524 status = "disabled"; 525 526 counter { 527 compatible = "renesas,rz-gtm-counter"; 528 status = "disabled"; 529 }; 530 }; 531 gtm1: gtm@42801400 { 532 compatible = "renesas,rz-gtm"; 533 reg = <0x42801400 0x30>; 534 channel = <1>; 535 interrupts = <45 1>; 536 interrupt-names = "overflow"; 537 status = "disabled"; 538 539 counter { 540 compatible = "renesas,rz-gtm-counter"; 541 status = "disabled"; 542 }; 543 }; 544 gtm2: gtm@42801800 { 545 compatible = "renesas,rz-gtm"; 546 reg = <0x42801800 0x30>; 547 channel = <2>; 548 interrupts = <46 1>; 549 interrupt-names = "overflow"; 550 status = "disabled"; 551 552 counter { 553 compatible = "renesas,rz-gtm-counter"; 554 status = "disabled"; 555 }; 556 }; 557 gtm3: gtm@42801c00 { 558 compatible = "renesas,rz-gtm"; 559 reg = <0x42801c00 0x30>; 560 channel = <3>; 561 interrupts = <47 1>; 562 interrupt-names = "overflow"; 563 status = "disabled"; 564 565 counter { 566 compatible = "renesas,rz-gtm-counter"; 567 status = "disabled"; 568 }; 569 }; 570 gtm4: gtm@42802000 { 571 compatible = "renesas,rz-gtm"; 572 reg = <0x42802000 0x30>; 573 channel = <4>; 574 interrupts = <48 1>; 575 interrupt-names = "overflow"; 576 status = "disabled"; 577 578 counter { 579 compatible = "renesas,rz-gtm-counter"; 580 status = "disabled"; 581 }; 582 }; 583 gtm5: gtm@42802400 { 584 compatible = "renesas,rz-gtm"; 585 reg = <0x42802400 0x30>; 586 channel = <5>; 587 interrupts = <49 1>; 588 interrupt-names = "overflow"; 589 status = "disabled"; 590 591 counter { 592 compatible = "renesas,rz-gtm-counter"; 593 status = "disabled"; 594 }; 595 }; 596 gtm6: gtm@42802800 { 597 compatible = "renesas,rz-gtm"; 598 reg = <0x42802800 0x30>; 599 channel = <6>; 600 interrupts = <50 1>; 601 interrupt-names = "overflow"; 602 status = "disabled"; 603 604 counter { 605 compatible = "renesas,rz-gtm-counter"; 606 status = "disabled"; 607 }; 608 }; 609 gtm7: gtm@42802c00 { 610 compatible = "renesas,rz-gtm"; 611 reg = <0x42802c00 0x30>; 612 channel = <7>; 613 interrupts = <51 1>; 614 interrupt-names = "overflow"; 615 status = "disabled"; 616 617 counter { 618 compatible = "renesas,rz-gtm-counter"; 619 status = "disabled"; 620 }; 621 }; 622 623 gpt32e0: gpt32e@50048000 { 624 compatible = "renesas,rz-gpt"; 625 reg = <0x50048000 0xa4>; 626 channel = <0>; 627 interrupts = <128 1>, <129 1>, <130 1>, <131 1>, <132 1>, 628 <133 1>, <134 1>, <135 1>, <136 1>, <137 1>; 629 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 630 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 631 prescaler = <1>; 632 status = "disabled"; 633 634 pwm { 635 compatible = "renesas,rz-gpt-pwm"; 636 #pwm-cells = <3>; 637 status = "disabled"; 638 }; 639 }; 640 gpt32e1: gpt32e@50048100 { 641 compatible = "renesas,rz-gpt"; 642 reg = <0x50048100 0xa4>; 643 channel = <1>; 644 interrupts = <141 1>, <142 1>, <143 1>, <144 1>, <145 1>, 645 <146 1>, <147 1>, <148 1>, <149 1>, <150 1>; 646 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 647 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 648 prescaler = <1>; 649 status = "disabled"; 650 651 pwm { 652 compatible = "renesas,rz-gpt-pwm"; 653 #pwm-cells = <3>; 654 status = "disabled"; 655 }; 656 }; 657 gpt32e2: gpt32e@50048200 { 658 compatible = "renesas,rz-gpt"; 659 reg = <0x50048200 0xa4>; 660 channel = <2>; 661 interrupts = <154 1>, <155 1>, <156 1>, <157 1>, <158 1>, 662 <159 1>, <160 1>, <161 1>, <162 1>, <163 1>; 663 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 664 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 665 prescaler = <1>; 666 status = "disabled"; 667 668 pwm { 669 compatible = "renesas,rz-gpt-pwm"; 670 #pwm-cells = <3>; 671 status = "disabled"; 672 }; 673 }; 674 gpt32e3: gpt32e@50048300 { 675 compatible = "renesas,rz-gpt"; 676 reg = <0x50048300 0xa4>; 677 channel = <3>; 678 interrupts = <167 1>, <168 1>, <169 1>, <170 1>, <171 1>, 679 <172 1>, <173 1>, <174 1>, <175 1>, <176 1>; 680 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 681 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 682 prescaler = <1>; 683 status = "disabled"; 684 685 pwm { 686 compatible = "renesas,rz-gpt-pwm"; 687 #pwm-cells = <3>; 688 status = "disabled"; 689 }; 690 }; 691 gpt32e4: gpt32e@50048400 { 692 compatible = "renesas,rz-gpt"; 693 reg = <0x50048400 0xa4>; 694 channel = <4>; 695 interrupts = <180 1>, <181 1>, <182 1>, <183 1>, <184 1>, 696 <185 1>, <186 1>, <187 1>, <188 1>, <189 1>; 697 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 698 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 699 prescaler = <1>; 700 status = "disabled"; 701 702 pwm { 703 compatible = "renesas,rz-gpt-pwm"; 704 #pwm-cells = <3>; 705 status = "disabled"; 706 }; 707 }; 708 gpt32e5: gpt32e@50048500 { 709 compatible = "renesas,rz-gpt"; 710 reg = <0x50048500 0xa4>; 711 channel = <5>; 712 interrupts = <193 1>, <194 1>, <195 1>, <196 1>, <197 1>, 713 <198 1>, <199 1>, <200 1>, <201 1>, <202 1>; 714 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 715 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 716 prescaler = <1>; 717 status = "disabled"; 718 719 pwm { 720 compatible = "renesas,rz-gpt-pwm"; 721 #pwm-cells = <3>; 722 status = "disabled"; 723 }; 724 }; 725 gpt32e6: gpt32e@50048600 { 726 compatible = "renesas,rz-gpt"; 727 reg = <0x50048600 0xa4>; 728 channel = <6>; 729 interrupts = <206 1>, <207 1>, <208 1>, <209 1>, <210 1>, 730 <211 1>, <212 1>, <213 1>, <214 1>, <215 1>; 731 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 732 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 733 prescaler = <1>; 734 status = "disabled"; 735 736 pwm { 737 compatible = "renesas,rz-gpt-pwm"; 738 #pwm-cells = <3>; 739 status = "disabled"; 740 }; 741 }; 742 gpt32e7: gpt32e@50048700 { 743 compatible = "renesas,rz-gpt"; 744 reg = <0x50048700 0xa4>; 745 channel = <7>; 746 interrupts = <219 1>, <220 1>, <221 1>, <222 1>, <223 1>, 747 <224 1>, <225 1>, <226 1>, <227 1>, <228 1>; 748 interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", 749 "cmpf", "adtrga", "adtrgb", "ovf", "unf"; 750 prescaler = <1>; 751 status = "disabled"; 752 753 pwm { 754 compatible = "renesas,rz-gpt-pwm"; 755 #pwm-cells = <3>; 756 status = "disabled"; 757 }; 758 }; 759 760 intc: interrupt-controller@41060000 { 761 reg = <0x41060000 0x18>; 762 #address-cells = <0>; 763 interrupt-parent = <&nvic>; 764 765 nmi: nmi { 766 compatible = "renesas,rz-ext-irq"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 interrupts = <0 1>; //NMI 770 status = "disabled"; 771 }; 772 773 irq0: irq0 { 774 compatible = "renesas,rz-ext-irq"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 interrupts = <1 1>; 778 status = "disabled"; 779 }; 780 irq1: irq1 { 781 compatible = "renesas,rz-ext-irq"; 782 interrupt-controller; 783 #interrupt-cells = <2>; 784 interrupts = <2 1>; 785 status = "disabled"; 786 }; 787 irq2: irq2 { 788 compatible = "renesas,rz-ext-irq"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 interrupts = <3 1>; 792 status = "disabled"; 793 }; 794 irq3: irq3 { 795 compatible = "renesas,rz-ext-irq"; 796 interrupt-controller; 797 #interrupt-cells = <2>; 798 interrupts = <4 1>; 799 status = "disabled"; 800 }; 801 irq4: irq4 { 802 compatible = "renesas,rz-ext-irq"; 803 interrupt-controller; 804 #interrupt-cells = <2>; 805 interrupts = <5 1>; 806 status = "disabled"; 807 }; 808 irq5: irq5 { 809 compatible = "renesas,rz-ext-irq"; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 interrupts = <6 1>; 813 status = "disabled"; 814 }; 815 irq6: irq6 { 816 compatible = "renesas,rz-ext-irq"; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 interrupts = <7 1>; 820 status = "disabled"; 821 }; 822 irq7: irq7 { 823 compatible = "renesas,rz-ext-irq"; 824 interrupt-controller; 825 #interrupt-cells = <2>; 826 interrupts = <8 1>; 827 status = "disabled"; 828 }; 829 }; 830 831 /* CM33 <-> CA55 */ 832 mbox1: mhu@50400020 { 833 compatible = "renesas,rz-mhu-mbox"; 834 channel = <1>; 835 reg = <0x50400020 0x20>; 836 tx-mask = <0x00000002>; /* Channel 1 is for TX */ 837 rx-mask = <0x00000001>; /* Channel 0 is for RX */ 838 channels-count = <2>; 839 interrupts = <58 2>; 840 interrupt-names = "mhuns"; 841 #mbox-cells = <1>; 842 status = "disabled"; 843 }; 844 845 /* CM33 <-> CM33_FPU */ 846 mbox3: mhu@50400060 { 847 compatible = "renesas,rz-mhu-mbox"; 848 channel = <3>; 849 reg = <0x50400060 0x20>; 850 tx-mask = <0x00000002>; /* Channel 1 is for TX */ 851 rx-mask = <0x00000001>; /* Channel 0 is for RX */ 852 channels-count = <2>; 853 interrupts = <59 2>; 854 interrupt-names = "mhuns"; 855 #mbox-cells = <1>; 856 status = "disabled"; 857 }; 858 859 /* CM33 <-> CA55 */ 860 mbox4: mhu@50400080 { 861 compatible = "renesas,rz-mhu-mbox"; 862 channel = <4>; 863 reg = <0x50400080 0x20>; 864 tx-mask = <0x00000002>; /* Channel 1 is for TX */ 865 rx-mask = <0x00000001>; /* Channel 0 is for RX */ 866 channels-count = <2>; 867 interrupts = <60 2>; 868 interrupt-names = "mhuns"; 869 #mbox-cells = <1>; 870 status = "disabled"; 871 }; 872 873 /* CM33 <-> CM33_FPU */ 874 mbox5: mhu@504000a0 { 875 compatible = "renesas,rz-mhu-mbox"; 876 channel = <5>; 877 reg = <0x504000a0 0x20>; 878 tx-mask = <0x00000002>; /* Channel 1 is for TX */ 879 rx-mask = <0x00000001>; /* Channel 0 is for RX */ 880 channels-count = <2>; 881 interrupts = <61 2>; 882 interrupt-names = "mhuns"; 883 #mbox-cells = <1>; 884 status = "disabled"; 885 }; 886 }; 887}; 888 889&nvic { 890 arm,num-irq-priority-bits = <7>; 891}; 892
