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Searched refs:P3_0 (Results 1 – 22 of 22) sorted by relevance

/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/pin_packages/
Dcyhal_cyw20829_56_qfn.c44 {0u, 0u, P3_0, HSIOM_SEL_GPIO},
106 {0u, 7u, P3_0, P3_0_KEYSCAN_KS_ROW7},
210 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0},
261 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0},
289 {2u, 0u, P3_0, P3_0_SCB2_UART_CTS},
361 {0u, 0u, P3_0, P3_0_TCPWM0_LINE0},
362 {1u, 0u, P3_0, P3_0_TCPWM0_LINE256},
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_psoc6_03_68_qfn.c84 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
119 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
173 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
247 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
317 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
374 {0u, 0u, P3_0, P3_0_SDHC0_IO_VOLT_SEL},
433 {0u, 3u, P3_0, P3_0_TCPWM0_LINE3},
434 {1u, 7u, P3_0, P3_0_TCPWM1_LINE7},
Dcyhal_psoc6_02_68_qfn.c122 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
158 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
218 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
302 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
386 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
457 {0u, 0u, P3_0, P3_0_SDHC0_IO_VOLT_SEL},
547 {0u, 2u, P3_0, P3_0_TCPWM0_LINE2},
548 {1u, 19u, P3_0, P3_0_TCPWM1_LINE19},
Dcyhal_psoc6_03_100_tqfp.c87 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
124 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
184 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
266 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
344 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
403 {0u, 0u, P3_0, P3_0_SDHC0_IO_VOLT_SEL},
462 {0u, 3u, P3_0, P3_0_TCPWM0_LINE3},
463 {1u, 7u, P3_0, P3_0_TCPWM1_LINE7},
Dcyhal_psoc6_04_68_qfn.c117 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
152 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
336 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
412 {0u, 3u, P3_0, P3_0_TCPWM0_LINE3},
413 {1u, 7u, P3_0, P3_0_TCPWM0_LINE263},
524 {1u, 1u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN257},
Dcyhal_psoc6_04_64_tqfp.c119 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
154 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
342 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
418 {0u, 3u, P3_0, P3_0_TCPWM0_LINE3},
419 {1u, 7u, P3_0, P3_0_TCPWM0_LINE263},
532 {1u, 1u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN257},
Dcyhal_psoc6_04_80_tqfp.c119 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
154 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
346 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
422 {0u, 3u, P3_0, P3_0_TCPWM0_LINE3},
423 {1u, 7u, P3_0, P3_0_TCPWM0_LINE263},
539 {1u, 1u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN257},
Dcyhal_psoc6_02_124_bga.c143 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
186 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
276 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
406 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
540 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
637 {0u, 0u, P3_0, P3_0_SDHC0_IO_VOLT_SEL},
733 {0u, 2u, P3_0, P3_0_TCPWM0_LINE2},
734 {1u, 19u, P3_0, P3_0_TCPWM1_LINE19},
Dcyhal_psoc6_02_128_tqfp.c143 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
186 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
277 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
409 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
546 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
643 {0u, 0u, P3_0, P3_0_SDHC0_IO_VOLT_SEL},
739 {0u, 2u, P3_0, P3_0_TCPWM0_LINE2},
740 {1u, 19u, P3_0, P3_0_TCPWM1_LINE19},
Dcyhal_psoc6_01_124_bga.c133 {0u, 0u, P3_0, P3_0_BLESS_MXD_DPSLP_DIG_LDO_EN},
257 {0u, 6u, P3_0, P3_0_PERI_TR_IO_INPUT6},
299 {2u, 0u, P3_0, P3_0_SCB2_I2C_SCL},
382 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
512 {2u, 0u, P3_0, P3_0_SCB2_SPI_MOSI},
637 {2u, 0u, P3_0, P3_0_SCB2_UART_RX},
757 {0u, 2u, P3_0, P3_0_TCPWM0_LINE2},
758 {1u, 19u, P3_0, P3_0_TCPWM1_LINE19},
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/include/pin_packages/
Dcyhal_cyw20829_56_qfn.h77 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/include/pin_packages/
Dcyhal_psoc6_04_68_qfn.h71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_04_80_tqfp.h75 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_03_68_qfn.h71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_04_64_tqfp.h71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_03_100_tqfp.h71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_02_68_qfn.h71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_02_124_bga.h78 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_02_128_tqfp.h78 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
Dcyhal_psoc6_01_124_bga.h78 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 enumerator
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc4_gpio_map.h114 #define P3_0 XMC_GPIO_PORT3, 0 macro
388 #define P3_0 XMC_GPIO_PORT3, 0 macro
651 #define P3_0 XMC_GPIO_PORT3, 0 macro
871 #define P3_0 XMC_GPIO_PORT3, 0 macro
1153 #define P3_0 XMC_GPIO_PORT3, 0 macro
1426 #define P3_0 XMC_GPIO_PORT3, 0 macro
1865 #define P3_0 XMC_GPIO_PORT3, 0 macro
2285 #define P3_0 XMC_GPIO_PORT3, 0 macro
2767 #define P3_0 XMC_GPIO_PORT3, 0 macro
3087 #define P3_0 XMC_GPIO_PORT3, 0 macro
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Dxmc1_gpio_map.h3006 #define P3_0 XMC_GPIO_PORT3, 0 macro
3357 #define P3_0 XMC_GPIO_PORT3, 0 macro
3621 #define P3_0 XMC_GPIO_PORT3, 0 macro
4226 #define P3_0 XMC_GPIO_PORT3, 0 macro
4501 #define P3_0 XMC_GPIO_PORT3, 0 macro
5267 #define P3_0 XMC_GPIO_PORT3, 0 macro
5468 #define P3_0 XMC_GPIO_PORT3, 0 macro
5735 #define P3_0 XMC_GPIO_PORT3, 0 macro
6456 #define P3_0 XMC_GPIO_PORT3, 0 macro
6822 #define P3_0 XMC_GPIO_PORT3, 0 macro