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Searched refs:P0_4 (Results 1 – 25 of 44) sorted by relevance

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/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/pin_packages/
Dcyhal_cyw20829_40_qfn.c79 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0},
120 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0},
153 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
186 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2},
196 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
229 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2},
315 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0},
316 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257},
358 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0},
Dcyhal_cyw20829_56_qfn.c102 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0},
151 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0},
186 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
225 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2},
237 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
276 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2},
383 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0},
384 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257},
434 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0},
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_psoc6_03_49_wlcsp.c76 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
96 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
125 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
190 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
265 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
374 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
375 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_04_68_qfn.c111 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
140 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
176 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
245 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
324 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
402 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
403 {1u, 2u, P0_4, P0_4_TCPWM0_LINE258},
514 {1u, 0u, P0_4, P0_4_TCPWM0_TR_ONE_CNT_IN256},
Dcyhal_psoc6_04_64_tqfp.c113 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
142 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
178 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
249 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
330 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
408 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
409 {1u, 2u, P0_4, P0_4_TCPWM0_LINE258},
522 {1u, 0u, P0_4, P0_4_TCPWM0_TR_ONE_CNT_IN256},
Dcyhal_psoc6_03_68_qfn.c78 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
107 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
145 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
219 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
304 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
423 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
424 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_04_80_tqfp.c113 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
142 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
178 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
251 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
334 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
412 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
413 {1u, 2u, P0_4, P0_4_TCPWM0_LINE258},
526 {1u, 0u, P0_4, P0_4_TCPWM0_TR_ONE_CNT_IN256},
Dcyhal_psoc6_03_100_tqfp.c81 {0u, 2u, P0_4, P0_4_PERI_TR_IO_INPUT2},
112 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
154 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
236 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
330 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
452 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
453 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_43_smt.c263 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
290 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
359 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
438 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
533 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
534 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_68_qfn_ble.c258 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
296 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
371 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
456 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
560 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
561 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_02_68_qfn.c145 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
187 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
271 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
369 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
537 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
538 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_80_wlcsp.c272 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
316 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
411 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
519 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
631 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
632 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_104_m_csp_ble_usb.c276 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
322 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
425 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
542 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
657 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
658 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_104_m_csp_ble.c276 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
322 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
426 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
545 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
660 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
661 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_116_bga_ble.c278 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
324 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
434 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
559 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
675 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
676 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_116_bga_usb.c278 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
324 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
431 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
552 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
668 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
669 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_02_100_wlcsp.c166 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
221 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
333 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
464 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
657 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
658 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_124_bga_sip.c280 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
326 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
441 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
572 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
689 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
690 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_02_124_bga.c172 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
232 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
362 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
514 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
717 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
718 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_02_128_tqfp.c172 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
232 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
364 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
519 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
723 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
724 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
Dcyhal_psoc6_01_124_bga.c286 {0u, 0u, P0_4, P0_4_PERI_TR_IO_OUTPUT0},
338 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
468 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK},
616 {0u, 0u, P0_4, P0_4_SCB0_UART_RTS},
741 {0u, 2u, P0_4, P0_4_TCPWM0_LINE2},
742 {1u, 2u, P0_4, P0_4_TCPWM1_LINE2},
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc1_gpio_map.h166 #define P0_4 XMC_GPIO_PORT0, 4 macro
358 #define P0_4 XMC_GPIO_PORT0, 4 macro
482 #define P0_4 XMC_GPIO_PORT0, 4 macro
696 #define P0_4 XMC_GPIO_PORT0, 4 macro
898 #define P0_4 XMC_GPIO_PORT0, 4 macro
1053 #define P0_4 XMC_GPIO_PORT0, 4 macro
1357 #define P0_4 XMC_GPIO_PORT0, 4 macro
1583 #define P0_4 XMC_GPIO_PORT0, 4 macro
1824 #define P0_4 XMC_GPIO_PORT0, 4 macro
2075 #define P0_4 XMC_GPIO_PORT0, 4 macro
[all …]
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/include/pin_packages/
Dcyhal_cyw20829_40_qfn.h55 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 enumerator
Dcyhal_cyw20829_56_qfn.h59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 enumerator
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/include/pin_packages/
Dcyhal_psoc6_03_49_wlcsp.h57 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 enumerator

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