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Searched refs:P0_3 (Results 1 – 25 of 38) sorted by relevance

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/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/pin_packages/
Dcyhal_cyw20829_56_qfn.c78 {0u, 12u, P0_3, P0_3_KEYSCAN_KS_COL12},
150 {0u, 5u, P0_3, P0_3_PERI_TR_IO_INPUT5},
178 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
193 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
231 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
244 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
282 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
351 {0u, 0u, P0_3, P0_3_TCPWM0_LINE0},
352 {1u, 1u, P0_3, P0_3_TCPWM0_LINE257},
424 {0u, 0u, P0_3, P0_3_TDM_TDM_RX_SD0},
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_psoc6_04_68_qfn.c163 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
187 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
256 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
346 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
456 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
457 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
513 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_04_64_tqfp.c165 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
189 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
260 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
352 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
463 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
464 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
521 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_04_80_tqfp.c165 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
189 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
262 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
356 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
467 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
468 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
525 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_03_68_qfn.c131 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
157 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
231 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
328 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
477 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
478 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_68_qfn_ble.c282 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
309 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
384 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
479 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
602 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
603 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_68_qfn.c171 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
201 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
285 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
398 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
589 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
590 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_03_100_tqfp.c138 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
167 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
249 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
356 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
518 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
519 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_80_wlcsp.c299 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
331 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
426 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
547 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
693 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
694 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_104_m_csp_ble_usb.c304 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
338 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
441 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
572 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
727 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
728 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_104_m_csp_ble.c304 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
338 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
442 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
575 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
730 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
731 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_116_bga_ble.c306 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
341 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
451 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
590 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
755 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
756 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_116_bga_usb.c306 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
341 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
448 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
583 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
746 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
747 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_100_wlcsp.c199 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
239 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
351 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
504 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
739 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
740 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_124_bga_sip.c308 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
344 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
459 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
604 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
773 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
774 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_124_bga.c207 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
252 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
382 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
559 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
817 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
818 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_128_tqfp.c207 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
253 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
385 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
565 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
825 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
826 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_124_bga.c317 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
358 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
488 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
653 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
841 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
842 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc1_gpio_map.h72 #define P0_3 XMC_GPIO_PORT0, 3 macro
165 #define P0_3 XMC_GPIO_PORT0, 3 macro
294 #define P0_3 XMC_GPIO_PORT0, 3 macro
357 #define P0_3 XMC_GPIO_PORT0, 3 macro
481 #define P0_3 XMC_GPIO_PORT0, 3 macro
695 #define P0_3 XMC_GPIO_PORT0, 3 macro
897 #define P0_3 XMC_GPIO_PORT0, 3 macro
1052 #define P0_3 XMC_GPIO_PORT0, 3 macro
1247 #define P0_3 XMC_GPIO_PORT0, 3 macro
1356 #define P0_3 XMC_GPIO_PORT0, 3 macro
[all …]
Dxmc4_gpio_map.h83 #define P0_3 XMC_GPIO_PORT0, 3 macro
245 #define P0_3 XMC_GPIO_PORT0, 3 macro
357 #define P0_3 XMC_GPIO_PORT0, 3 macro
513 #define P0_3 XMC_GPIO_PORT0, 3 macro
620 #define P0_3 XMC_GPIO_PORT0, 3 macro
749 #define P0_3 XMC_GPIO_PORT0, 3 macro
840 #define P0_3 XMC_GPIO_PORT0, 3 macro
1002 #define P0_3 XMC_GPIO_PORT0, 3 macro
1114 #define P0_3 XMC_GPIO_PORT0, 3 macro
1387 #define P0_3 XMC_GPIO_PORT0, 3 macro
[all …]
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/include/pin_packages/
Dcyhal_cyw20829_56_qfn.h58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 enumerator
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/include/pin_packages/
Dcyhal_psoc6_04_68_qfn.h58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 enumerator
Dcyhal_psoc6_04_80_tqfp.h58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 enumerator
Dcyhal_psoc6_03_68_qfn.h58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 enumerator
Dcyhal_psoc6_04_64_tqfp.h58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 enumerator

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