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Searched refs:P0_1 (Results 1 – 25 of 43) sorted by relevance

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/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/pin_packages/
Dcyhal_cyw20829_56_qfn.c76 {0u, 4u, P0_1, P0_1_KEYSCAN_KS_COL4},
139 {0u, 1u, P0_1, P0_1_PDM_PDM_DATA1},
224 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
275 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
349 {0u, 1u, P0_1, P0_1_TCPWM0_LINE1},
350 {1u, 0u, P0_1, P0_1_TCPWM0_LINE256},
419 {0u, 0u, P0_1, P0_1_TDM_TDM_RX_SCK0},
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_psoc6_03_49_wlcsp.c75 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
177 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
242 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
416 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
417 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_04_68_qfn.c110 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
230 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
299 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
454 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
455 {1u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL256},
511 {0u, 1u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN1},
Dcyhal_psoc6_04_64_tqfp.c112 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
233 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
304 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
461 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
462 {1u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL256},
519 {0u, 1u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN1},
Dcyhal_psoc6_04_80_tqfp.c112 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
234 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
307 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
465 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
466 {1u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL256},
523 {0u, 1u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN1},
Dcyhal_psoc6_03_68_qfn.c77 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
205 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
279 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
475 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
476 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_43_smt.c246 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
343 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
412 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
573 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
574 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_68_qfn_ble.c238 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
357 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
432 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
600 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
601 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_02_68_qfn.c119 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
254 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
338 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
587 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
588 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_03_100_tqfp.c80 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
219 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
301 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
516 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
517 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_80_wlcsp.c246 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
393 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
488 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
691 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
692 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_104_m_csp_ble_usb.c248 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
403 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
506 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
725 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
726 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_104_m_csp_ble.c248 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
404 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
508 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
728 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
729 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_116_bga_ble.c250 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
408 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
518 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
753 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
754 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_116_bga_usb.c250 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
406 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
513 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
744 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
745 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_02_100_wlcsp.c136 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
310 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
422 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
737 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
738 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_124_bga_sip.c252 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
413 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
528 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
771 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
772 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_02_124_bga.c138 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
331 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
461 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
815 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
816 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_02_128_tqfp.c138 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
333 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
465 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
823 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
824 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
Dcyhal_psoc6_01_124_bga.c252 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1},
437 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
567 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2},
839 {0u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL0},
840 {1u, 0u, P0_1, P0_1_TCPWM1_LINE_COMPL0},
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc1_gpio_map.h70 #define P0_1 XMC_GPIO_PORT0, 1 macro
163 #define P0_1 XMC_GPIO_PORT0, 1 macro
292 #define P0_1 XMC_GPIO_PORT0, 1 macro
355 #define P0_1 XMC_GPIO_PORT0, 1 macro
479 #define P0_1 XMC_GPIO_PORT0, 1 macro
693 #define P0_1 XMC_GPIO_PORT0, 1 macro
895 #define P0_1 XMC_GPIO_PORT0, 1 macro
1050 #define P0_1 XMC_GPIO_PORT0, 1 macro
1245 #define P0_1 XMC_GPIO_PORT0, 1 macro
1354 #define P0_1 XMC_GPIO_PORT0, 1 macro
[all …]
Dxmc4_gpio_map.h81 #define P0_1 XMC_GPIO_PORT0, 1 macro
243 #define P0_1 XMC_GPIO_PORT0, 1 macro
355 #define P0_1 XMC_GPIO_PORT0, 1 macro
511 #define P0_1 XMC_GPIO_PORT0, 1 macro
618 #define P0_1 XMC_GPIO_PORT0, 1 macro
747 #define P0_1 XMC_GPIO_PORT0, 1 macro
838 #define P0_1 XMC_GPIO_PORT0, 1 macro
1000 #define P0_1 XMC_GPIO_PORT0, 1 macro
1112 #define P0_1 XMC_GPIO_PORT0, 1 macro
1385 #define P0_1 XMC_GPIO_PORT0, 1 macro
[all …]
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1A/include/pin_packages/
Dcyhal_psoc6_03_49_wlcsp.h56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 enumerator
Dcyhal_psoc6_04_68_qfn.h56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 enumerator
/hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/include/pin_packages/
Dcyhal_cyw20829_56_qfn.h56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 enumerator

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