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Searched refs:channel (Results 1 – 25 of 27) sorted by relevance

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/hal_infineon-2.7.6/XMCLib/drivers/inc/
Dxmc_spi.h371 void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config);
386 __STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel) in XMC_SPI_CH_Start() argument
389 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_SPI); in XMC_SPI_CH_Start()
407 XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel);
423 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
440 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, boo…
458 void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t sla…
472 void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel);
489 __STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE… in XMC_SPI_CH_SetTransmitMode() argument
491 channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | in XMC_SPI_CH_SetTransmitMode()
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Dxmc_usic.h577 __STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel) in XMC_USIC_IsChannelValid() argument
581 tmp = ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)); in XMC_USIC_IsChannelValid()
583 tmp = tmp || ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)); in XMC_USIC_IsChannelValid()
586 tmp = tmp || ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)); in XMC_USIC_IsChannelValid()
635 void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel);
648 void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel);
671 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t …
693 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, int32_t rate, int32_t …
709 uint32_t XMC_USIC_CH_GetBaudrate(XMC_USIC_CH_t *const channel);
724 uint32_t XMC_USIC_CH_GetSCLKFrequency(XMC_USIC_CH_t *const channel);
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Dxmc_i2s.h280 void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config);
295 __STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel) in XMC_I2S_CH_Start() argument
298 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S); in XMC_I2S_CH_Start()
316 XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel);
332 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
349 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, boo…
362 void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_l…
381 void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNE…
398 __STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t ch… in XMC_I2S_CH_Receive() argument
401 XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number); in XMC_I2S_CH_Receive()
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Dxmc_uart.h268 void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config);
284 __STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel) in XMC_UART_CH_Start() argument
286 …channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERA… in XMC_UART_CH_Start()
304 XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel);
329 XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t …
355 XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_…
378 void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data);
394 uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
416 __STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_len… in XMC_UART_CH_SetWordLength() argument
418 XMC_USIC_CH_SetWordLength(channel, word_length); in XMC_UART_CH_SetWordLength()
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Dxmc_dac.h502 void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const …
521 __STATIC_INLINE void XMC_DAC_CH_EnableOutput(XMC_DAC_t *const dac, const uint8_t channel) in XMC_DAC_CH_EnableOutput() argument
524 …SSERT("XMC_DAC_CH_EnableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); in XMC_DAC_CH_EnableOutput()
526 dac->DACCFG[channel].high |= DAC_DAC0CFG1_ANAEN_Msk; in XMC_DAC_CH_EnableOutput()
545 __STATIC_INLINE void XMC_DAC_CH_DisableOutput(XMC_DAC_t *const dac, const uint8_t channel) in XMC_DAC_CH_DisableOutput() argument
548 …SERT("XMC_DAC_CH_DisableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); in XMC_DAC_CH_DisableOutput()
550 dac->DACCFG[channel].high &= ~DAC_DAC0CFG1_ANAEN_Msk; in XMC_DAC_CH_DisableOutput()
571 __STATIC_INLINE bool XMC_DAC_CH_IsOutputEnabled(const XMC_DAC_t *const dac, const uint8_t channel) in XMC_DAC_CH_IsOutputEnabled() argument
574 …RT("XMC_DAC_CH_IsOutputEnabled: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); in XMC_DAC_CH_IsOutputEnabled()
576 return (bool)(dac->DACCFG[channel].high & DAC_DAC0CFG1_ANAEN_Msk); in XMC_DAC_CH_IsOutputEnabled()
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Dxmc_i2c.h294 void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config);
311 XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
329 XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, bool norm…
345 __STATIC_INLINE void XMC_I2C_CH_Start(XMC_USIC_CH_t *const channel) in XMC_I2C_CH_Start() argument
347 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2C); in XMC_I2C_CH_Start()
364 XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel);
384 __STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, in XMC_I2C_CH_SetInterruptNodePointer() argument
387 …XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_… in XMC_I2C_CH_SetInterruptNodePointer()
410 __STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, in XMC_I2C_CH_SelectInterruptNodePointer() argument
414 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, in XMC_I2C_CH_SelectInterruptNodePointer()
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Dxmc_dsd.h674 void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *co…
690 XMC_DSD_STATUS_t XMC_DSD_CH_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const init…
709 __STATIC_INLINE void XMC_DSD_Start(XMC_DSD_t *const dsd, const uint32_t channel) in XMC_DSD_Start() argument
712 dsd->GLOBRC |= channel; in XMC_DSD_Start()
730 __STATIC_INLINE void XMC_DSD_Stop(XMC_DSD_t *const dsd, const uint32_t channel) in XMC_DSD_Stop() argument
733 dsd->GLOBRC &= (uint32_t) ~channel; in XMC_DSD_Stop()
747 __STATIC_INLINE bool XMC_DSD_IsChannelStarted(XMC_DSD_t *const dsd, const XMC_DSD_CH_ID_t channel) in XMC_DSD_IsChannelStarted() argument
751 if (dsd->GLOBRC & (uint32_t)channel) in XMC_DSD_IsChannelStarted()
774 __STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) in XMC_DSD_CH_GetResult() argument
777 result = (uint16_t)((uint32_t)channel->RESM & DSD_CH_RESM_RESULT_Msk); in XMC_DSD_CH_GetResult()
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Dxmc_dma.h727 XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_C…
742 __STATIC_INLINE void XMC_DMA_CH_Enable(XMC_DMA_t *const dma, const uint8_t channel) in XMC_DMA_CH_Enable() argument
744 dma->CHENREG = (uint32_t)(0x101UL << channel); in XMC_DMA_CH_Enable()
758 void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel);
773 bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel);
791 void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel);
809 void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel);
827 __STATIC_INLINE void XMC_DMA_CH_SetSourceAddress(XMC_DMA_t *const dma, const uint8_t channel, uint3… in XMC_DMA_CH_SetSourceAddress() argument
829 dma->CH[channel].SAR = addr; in XMC_DMA_CH_SetSourceAddress()
848 __STATIC_INLINE void XMC_DMA_CH_SetDestinationAddress(XMC_DMA_t *const dma, const uint8_t channel, … in XMC_DMA_CH_SetDestinationAddress() argument
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Dxmc_eru.h502 void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *cons…
526 const uint8_t channel,
548 const uint8_t channel,
567 const uint8_t channel,
583 const uint8_t channel);
600 __STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) in XMC_ERU_ETL_SetStatusFlag() argument
603 XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Channel Number", (channel < 4U)); in XMC_ERU_ETL_SetStatusFlag()
605 eru->EXICON_b[channel].FL = true; in XMC_ERU_ETL_SetStatusFlag()
623 __STATIC_INLINE void XMC_ERU_ETL_ClearStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) in XMC_ERU_ETL_ClearStatusFlag() argument
626 XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Channel Number", (channel < 4U)); in XMC_ERU_ETL_ClearStatusFlag()
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Dxmc_bccu.h1317 void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config);
1336 void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_…
1406 void XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div);
1439 void XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int);
1452 uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel);
1474 void XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, ui…
1489 void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val);
1506 void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1523 void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level);
1536 __STATIC_INLINE uint32_t XMC_BCCU_CH_ReadPackerThreshold (XMC_BCCU_CH_t *const channel) in XMC_BCCU_CH_ReadPackerThreshold() argument
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Dxmc_ccu8.h1646 const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel,
2249 const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel,
2319 const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel);
3007 const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel,
3042 …ICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_STATUS_t channel);
3241 …it(XMC_CCU8_MODULE_t *const module, uint8_t slice_number, XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) in XMC_CCU8_GetSliceStatusBit() argument
3243 …ATUS_BIT_t)((module->GCST & ((CCU8_GCST_CC80ST1_Msk << slice_number) << (channel * CCU8_GCST_CC80S… in XMC_CCU8_GetSliceStatusBit()
Dxmc_ecat.h388 void XMC_ECAT_DisableSyncManChannel(const uint8_t channel);
400 void XMC_ECAT_EnableSyncManChannel(const uint8_t channel);
/hal_infineon-2.7.6/XMCLib/drivers/src/
Dxmc_i2c.c114 void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config) in XMC_I2C_CH_Init() argument
116 XMC_USIC_CH_Enable(channel); in XMC_I2C_CH_Init()
119 …channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision m… in XMC_I2C_CH_Init()
125 XMC_I2C_CH_SetSlaveAddress(channel, config->address); in XMC_I2C_CH_Init()
126 (void)XMC_I2C_CH_SetBaudrateEx(channel, config->baudrate, config->normal_divider_mode); in XMC_I2C_CH_Init()
130 channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk; in XMC_I2C_CH_Init()
133 channel->PSCR = 0xFFFFFFFFU; in XMC_I2C_CH_Init()
136 channel->CCR = 0x0U; in XMC_I2C_CH_Init()
139 void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address) in XMC_I2C_CH_SetSlaveAddress() argument
143 channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U); in XMC_I2C_CH_SetSlaveAddress()
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Dxmc_usic.c93 void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel) in XMC_USIC_CH_Enable() argument
95 XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel)); in XMC_USIC_CH_Enable()
97 if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)) in XMC_USIC_CH_Enable()
102 else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)) in XMC_USIC_CH_Enable()
108 else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)) in XMC_USIC_CH_Enable()
119 channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk); in XMC_USIC_CH_Enable()
120 while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U) in XMC_USIC_CH_Enable()
126 channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk; in XMC_USIC_CH_Enable()
129 void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel) in XMC_USIC_CH_Disable() argument
131 …channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_… in XMC_USIC_CH_Disable()
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Dxmc_dma.c308 void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel) in XMC_DMA_CH_Disable() argument
310 dma->CHENREG = (uint32_t)(0x100UL << channel); in XMC_DMA_CH_Disable()
311 while((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U) in XMC_DMA_CH_Disable()
318 bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel) in XMC_DMA_CH_IsEnabled() argument
320 return (bool)(dma->CHENREG & ((uint32_t)1U << channel)); in XMC_DMA_CH_IsEnabled()
324 XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_C… in XMC_DMA_CH_Init() argument
332 if (XMC_DMA_CH_IsEnabled(dma, channel) == false) in XMC_DMA_CH_Init()
334 dma->CH[channel].SAR = config->src_addr; in XMC_DMA_CH_Init()
335 dma->CH[channel].DAR = config->dst_addr; in XMC_DMA_CH_Init()
336 dma->CH[channel].LLP = (uint32_t)config->linked_list_pointer; in XMC_DMA_CH_Init()
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Dxmc_eru.c100 #define XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(channel) \ argument
101 ((channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0) || \
102 (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1) || \
103 (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2) || \
104 (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3))
128 const uint8_t channel, in XMC_ERU_ETL_Init() argument
132 XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U)); in XMC_ERU_ETL_Init()
137 … ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | in XMC_ERU_ETL_Init()
138 (config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE)); in XMC_ERU_ETL_Init()
140 eru->EXICON[channel] = config->raw; in XMC_ERU_ETL_Init()
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Dxmc_spi.c83 void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config) in XMC_SPI_CH_Init() argument
85 XMC_USIC_CH_Enable(channel); in XMC_SPI_CH_Init()
93 (void)XMC_USIC_CH_SetBaudrateEx(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); in XMC_SPI_CH_Init()
98 (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); in XMC_SPI_CH_Init()
105 channel->SCTR = USIC_CH_SCTR_PDL_Msk | in XMC_SPI_CH_Init()
113 channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk | in XMC_SPI_CH_Init()
120 channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk | in XMC_SPI_CH_Init()
127 channel->PSCR = 0xFFFFFFFFUL; in XMC_SPI_CH_Init()
130 channel->CCR = (uint32_t)config->parity_mode; in XMC_SPI_CH_Init()
133 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) in XMC_SPI_CH_SetBaudrate() argument
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Dxmc_i2s.c91 void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config) in XMC_I2S_CH_Init() argument
95 XMC_USIC_CH_Enable(channel); in XMC_I2S_CH_Init()
100 (void)XMC_I2S_CH_SetBaudrateEx(channel, config->baudrate, config->normal_divider_mode); in XMC_I2S_CH_Init()
104 channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) | in XMC_I2S_CH_Init()
113 channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | in XMC_I2S_CH_Init()
124 channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk; in XMC_I2S_CH_Init()
128 channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk | in XMC_I2S_CH_Init()
132 XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length); in XMC_I2S_CH_Init()
135 channel->PSCR = 0xFFFFFFFFUL; in XMC_I2S_CH_Init()
139 XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) in XMC_I2S_CH_SetBaudrate() argument
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Dxmc_dac.c119 void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const … in XMC_DAC_CH_Init() argument
123 dac->DACCFG[channel].low = config->cfg0; in XMC_DAC_CH_Init()
124 dac->DACCFG[channel].high = config->cfg1; in XMC_DAC_CH_Init()
125 if (channel < XMC_DAC_NO_CHANNELS) in XMC_DAC_CH_Init()
127 XMC_DAC_CH_EnableOutput(dac, channel); in XMC_DAC_CH_Init()
133 const uint8_t channel, in XMC_DAC_CH_SetFrequency() argument
152 dac->DACCFG[channel].low = (dac->DACCFG[channel].low & (uint32_t)(~DAC_DAC0CFG0_FREQ_Msk)) | in XMC_DAC_CH_SetFrequency()
162 const uint8_t channel, in XMC_DAC_CH_SetRampFrequency() argument
168 start = dac->DACDATA[channel]; in XMC_DAC_CH_SetRampFrequency()
169 …stop = (dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & (uint32_t)DAC_DAC01DATA_DATA0_Msk; in XMC_DAC_CH_SetRampFrequency()
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Dxmc_uart.c84 void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config) in XMC_UART_CH_Init() argument
89 XMC_USIC_CH_Enable(channel); in XMC_UART_CH_Init()
100 (void)XMC_USIC_CH_SetBaudrateEx(channel, config->baudrate, oversampling); in XMC_UART_CH_Init()
105 (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling); in XMC_UART_CH_Init()
116 channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) | in XMC_UART_CH_Init()
126 channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) | in XMC_UART_CH_Init()
131 channel->SCTR |= (uint32_t)(((uint32_t)config->frame_length - 1UL) << USIC_CH_SCTR_FLE_Pos); in XMC_UART_CH_Init()
135 channel->SCTR |= (uint32_t)(((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_FLE_Pos); in XMC_UART_CH_Init()
139 channel->TCSR = (0x1UL << USIC_CH_TCSR_TDEN_Pos) | in XMC_UART_CH_Init()
143 channel->PSCR = 0xFFFFFFFFUL; in XMC_UART_CH_Init()
[all …]
Dxmc_dsd.c185 XMC_DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const con… in XMC_DSD_CH_Init() argument
189 XMC_ASSERT("XMC_DSD_CH_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); in XMC_DSD_CH_Init()
194 XMC_DSD_CH_MainFilter_Init(channel, config->filter); in XMC_DSD_CH_Init()
198 XMC_DSD_CH_AuxFilter_Init(channel, config->aux); in XMC_DSD_CH_Init()
202 XMC_DSD_CH_Integrator_Init(channel, config->integrator); in XMC_DSD_CH_Init()
206 XMC_DSD_CH_Rectify_Init(channel, config->rectify); in XMC_DSD_CH_Init()
210 XMC_DSD_CH_Timestamp_Init(channel, config->timestamp); in XMC_DSD_CH_Init()
223 void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *cons… in XMC_DSD_CH_MainFilter_Init() argument
228 XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); in XMC_DSD_CH_MainFilter_Init()
236 …channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_M… in XMC_DSD_CH_MainFilter_Init()
[all …]
Dxmc_bccu.c402 void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config) in XMC_BCCU_CH_Init() argument
404 channel->CHCONFIG = config->chconfig; in XMC_BCCU_CH_Init()
406 channel->PKCMP = config->pkcmp; in XMC_BCCU_CH_Init()
408 channel->PKCNTR = config->pkcntr; in XMC_BCCU_CH_Init()
414 void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_… in XMC_BCCU_CH_ConfigTrigger() argument
417 channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_TRED_Msk | BCCU_CH_CHCONFIG_ENFT_Msk); in XMC_BCCU_CH_ConfigTrigger()
421 channel->CHCONFIG |= reg; in XMC_BCCU_CH_ConfigTrigger()
427 void XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div) in XMC_BCCU_CH_SetLinearWalkPrescaler() argument
429 channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_LINPRES_Msk); in XMC_BCCU_CH_SetLinearWalkPrescaler()
430 channel->CHCONFIG |= (uint32_t)(clk_div << BCCU_CH_CHCONFIG_LINPRES_Pos); in XMC_BCCU_CH_SetLinearWalkPrescaler()
[all …]
Dxmc_ccu8.c159 #define XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel) \ argument
160 ((channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE) || \
161 (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1) || \
162 (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_2) || \
163 (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2))
166 #define XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel) \ argument
167 ((channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1) || \
168 (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_2) || \
169 (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2) || \
170 (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2))
[all …]
Dxmc_ecat.c140 void XMC_ECAT_DisableSyncManChannel(const uint8_t channel) in XMC_ECAT_DisableSyncManChannel() argument
142 ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U; in XMC_ECAT_DisableSyncManChannel()
146 void XMC_ECAT_EnableSyncManChannel(const uint8_t channel) in XMC_ECAT_EnableSyncManChannel() argument
148 …((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(… in XMC_ECAT_EnableSyncManChannel()
Dxmc_usbh.c346 uint32_t channel; in XMC_USBH_Initialize() local
359 for (channel = 0U; channel < USBH0_MAX_PIPE_NUM; channel++) { in XMC_USBH_Initialize()
360 … XMC_USBH0_dfifo_ptr[channel] = (uint32_t *)((uint32_t)USB0_BASE + ((channel + 1U) * 0x01000U)); in XMC_USBH_Initialize()

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