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/hal_gigadevice-latest/gd32vf103/riscv/drivers/
Driscv_encoding.h207 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
208 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
209 __asm__ volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
211 __asm__ volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
214 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
215 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
216 __asm__ volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
218 __asm__ volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \