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Searched refs:SPI_CTL1 (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_spi.c136 reg3 = SPI_CTL1(spi_periph); in spi_init()
182 SPI_CTL1(spi_periph) = (uint32_t)reg3; in spi_init()
389 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
400 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
438 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
440 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
457 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
459 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
486 reg = SPI_CTL1(spi_periph); in spi_i2s_data_frame_format_config()
491 SPI_CTL1(spi_periph) = reg; in spi_i2s_data_frame_format_config()
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_spi.c336 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
347 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
385 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
387 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
404 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
406 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
559 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
570 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
581 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
592 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_spi.c299 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
310 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
348 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
350 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
367 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
369 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
520 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
531 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
542 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
553 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_spi.c344 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
355 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
393 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
395 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
412 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
414 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
566 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
577 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
588 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
599 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_spi.c353 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
364 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
402 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
404 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
421 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
423 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
573 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
584 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
595 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
606 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_spi.c339 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
350 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
388 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
390 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
407 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
409 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
561 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
572 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
583 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
594 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_spi.c354 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
365 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
403 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
405 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
422 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
424 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
573 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
584 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
725 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; in spi_i2s_interrupt_enable()
729 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; in spi_i2s_interrupt_enable()
[all …]
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_spi.c361 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
372 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
410 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
412 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
429 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
431 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
583 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
594 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
605 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
616 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_spi.h48 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_spi.h49 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_spi.h48 #define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_spi.h52 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_spi.h58 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_spi.h53 #define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_spi.h46 #define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control re… macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_spi.h46 #define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control re… macro