| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_rcu.c | 99 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
129 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
143 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
157 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
183 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
209 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
607 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
643 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
667 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); in rcu_interrupt_flag_clear()
686 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_rcu.c | 126 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
170 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
217 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
264 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
301 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
338 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
766 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { in rcu_flag_get()
803 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { in rcu_interrupt_flag_get()
828 RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); in rcu_interrupt_flag_clear()
848 RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_rcu.c | 102 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
133 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
161 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
189 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
203 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
217 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
658 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); in rcu_osci_on()
675 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); in rcu_osci_off()
1052 if(0U != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { in rcu_flag_get()
1088 if(0U != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { in rcu_interrupt_flag_get()
[all …]
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_rcu.c | 119 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
151 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
165 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
179 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
206 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
233 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
693 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
730 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
755 RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); in rcu_interrupt_flag_clear()
775 RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_rcu.c | 125 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
155 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
169 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
183 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
209 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
235 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
696 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
733 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
758 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); in rcu_interrupt_flag_clear()
778 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_rcu.c | 105 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
142 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
157 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
172 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
203 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
235 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
686 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { in rcu_flag_get()
721 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { in rcu_interrupt_flag_get()
745 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); in rcu_interrupt_flag_clear()
764 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_rcu.c | 105 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
134 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
148 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
162 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
187 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
213 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
620 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
655 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
679 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); in rcu_interrupt_flag_clear()
698 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_rcu.c | 162 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_enable()
202 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_disable()
216 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_enable()
230 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); in rcu_periph_clock_sleep_disable()
262 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_enable()
294 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); in rcu_periph_reset_disable()
968 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ in rcu_flag_get()
1006 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ in rcu_interrupt_flag_get()
1032 RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); in rcu_interrupt_flag_clear()
1053 RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); in rcu_interrupt_enable()
[all …]
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 235 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 253 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_rcu.h | 255 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) macro
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 271 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 278 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_rcu.h | 257 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) macro
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_rcu.h | 447 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 497 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) macro
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