| /hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/source/ |
| D | system_gd32a50x.c | 237 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC8M) { in system_clock_8m_irc8m()
296 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_24m_pll_irc8m()
357 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_48m_pll_irc8m()
417 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_72m_pll_irc8m()
477 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_100m_pll_irc8m()
524 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_HXTAL) { in system_clock_hxtal()
584 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_24m_pll_hxtal()
644 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_48m_pll_hxtal()
704 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_72m_pll_hxtal()
764 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_100m_pll_hxtal()
[all …]
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| /hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/source/ |
| D | system_gd32l23x.c | 162 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_HXTAL) { in system_clock_8m_hxtal()
220 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_64m_hxtal()
280 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { in system_clock_64m_irc16m()
305 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC16M) { in system_clock_16m_irc16m()
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_rcu.c | 61 while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC8M) { in rcu_deinit()
272 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
915 sws = RCU_CFG0 & RCU_CFG0_SCSS; in rcu_clock_freq_get()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_rcu.c | 265 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_rcu.c | 394 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 143 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
159 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
175 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_rcu.c | 289 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_rcu.c | 291 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_rcu.c | 292 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_rcu.c | 269 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_rcu.c | 350 return (RCU_CFG0 & RCU_CFG0_SCSS); in rcu_system_clock_source_get()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 80 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 78 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock swi… macro
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_rcu.h | 82 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 84 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 83 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_rcu.h | 82 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_rcu.h | 106 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ macro
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