Searched refs:CFG1_PREDV1 (Results 1 – 4 of 4) sorted by relevance
559 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) macro560 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input sourc…561 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input sourc…562 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input sourc…563 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input sourc…564 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input sourc…565 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input sourc…566 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input sourc…567 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input sourc…568 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input sourc…[all …]
652 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) macro653 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input sourc…654 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input sourc…655 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input sourc…656 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input sourc…657 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input sourc…658 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input sourc…659 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input sourc…660 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input sourc…661 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input sourc…[all …]
691 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) macro692 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input sourc…693 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input sourc…694 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input sourc…695 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input sourc…696 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input sourc…697 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input sourc…698 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input sourc…699 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input sourc…700 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input sourc…[all …]
1024 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) macro1025 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input sourc…1026 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input sourc…1027 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input sourc…1028 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input sourc…1029 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input sourc…1030 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input sourc…1031 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input sourc…1032 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input sourc…1033 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input sourc…[all …]
