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Searched refs:RCU_TIMER9RST (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_timer.c101 rcu_periph_reset_enable(RCU_TIMER9RST); in timer_deinit()
102 rcu_periph_reset_disable(RCU_TIMER9RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_timer.c85 rcu_periph_reset_enable(RCU_TIMER9RST); in timer_deinit()
86 rcu_periph_reset_disable(RCU_TIMER9RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_timer.c97 rcu_periph_reset_enable(RCU_TIMER9RST); in timer_deinit()
98 rcu_periph_reset_disable(RCU_TIMER9RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_timer.c101 rcu_periph_reset_enable(RCU_TIMER9RST); in timer_deinit()
102 rcu_periph_reset_disable(RCU_TIMER9RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_rcu.h412 … RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_rcu.h420 … RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_rcu.h719 … RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 17U), /*!< TIMER9 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_rcu.h699 … RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ enumerator