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Searched refs:RCU_TIMER3RST (Results 1 – 10 of 10) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_timer.c70 rcu_periph_reset_enable(RCU_TIMER3RST); in timer_deinit()
71 rcu_periph_reset_disable(RCU_TIMER3RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_timer.c60 rcu_periph_reset_enable(RCU_TIMER3RST); in timer_deinit()
61 rcu_periph_reset_disable(RCU_TIMER3RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_timer.c67 rcu_periph_reset_enable(RCU_TIMER3RST); in timer_deinit()
68 rcu_periph_reset_disable(RCU_TIMER3RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_timer.c71 rcu_periph_reset_enable(RCU_TIMER3RST); in timer_deinit()
72 rcu_periph_reset_disable(RCU_TIMER3RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_timer.c68 rcu_periph_reset_enable(RCU_TIMER3RST); in timer_deinit()
69 rcu_periph_reset_disable(RCU_TIMER3RST); in timer_deinit()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_rcu.h319 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_rcu.h376RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_rcu.h381RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_rcu.h685RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ enumerator
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_rcu.h645RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ enumerator