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Searched refs:EXMC_SNCTL_CPS (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_exmc.h67 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_exmc.c229 EXMC_SNCTL &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_exmc.c287 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_exmc.h97 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_exmc.h97 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_exmc.c488 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_exmc.c752 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_exmc.h121 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ macro