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Searched refs:vaddr_end (Results 1 – 16 of 16) sorted by relevance

/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dcache_ll.h67 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
72 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
75 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()
76 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
79 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
80 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()
81 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
84 mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0; in cache_ll_l1_get_bus()
85 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
86 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()
[all …]
Dmmu_ll.h97 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
101 …tart >= DROM0_ADDRESS_LOW) && (vaddr_end < DROM0_ADDRESS_HIGH)) || ((vaddr_start >= DPORT_CACHE_AD… in mmu_ll_check_valid_ext_vaddr_region()
105 valid |= ((vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < IRAM1_ADDRESS_HIGH)); in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h100 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
107 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
110 mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
111 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
113 …HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, se… in cache_ll_l1_get_bus()
116 …HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, se… in cache_ll_l1_get_bus()
Dmmu_ll.h99 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
103 valid |= (ADDRESS_IN_DRAM1_CACHE(vaddr_start) && ADDRESS_IN_DRAM1_CACHE(vaddr_end)) || in mmu_ll_check_valid_ext_vaddr_region()
104 (ADDRESS_IN_DROM0_CACHE(vaddr_start) && ADDRESS_IN_DROM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
108 valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || in mmu_ll_check_valid_ext_vaddr_region()
109 (ADDRESS_IN_IRAM1_CACHE(vaddr_start) && ADDRESS_IN_IRAM1_CACHE(vaddr_end)) || in mmu_ll_check_valid_ext_vaddr_region()
110 (ADDRESS_IN_IROM0_CACHE(vaddr_start) && ADDRESS_IN_IROM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/esp_psram/
Desp_psram.c68 intptr_t vaddr_end; member
223 …s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + si… in esp_psram_init()
226 …s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + s… in esp_psram_init()
258 …s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + … in esp_psram_init()
261 …s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned +… in esp_psram_init()
315 … s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end); in esp_psram_extram_add_to_heap_allocator()
325 … s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end); in esp_psram_extram_add_to_heap_allocator()
344 …GNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end) || in esp_psram_check_ptr_addr()
345 …IGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end); in esp_psram_check_ptr_addr()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h71 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
72 if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
74 } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
Dmmu_ll.h96 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
100 valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
104 valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h72 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
73 if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
75 } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
Dmmu_ll.h97 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
101 valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
105 valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h83 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
84 if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
86 } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
Dmmu_ll.h97 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
101 valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
105 valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end)); in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dcache_ll.h46 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
47 if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
Dmmu_ll.h108 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
109 …start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN… in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h46 uint32_t vaddr_end = vaddr_start + len - 1; in cache_ll_l1_get_bus() local
47 if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { in cache_ll_l1_get_bus()
Dmmu_ll.h105 uint32_t vaddr_end = vaddr_start + len - 1; in mmu_ll_check_valid_ext_vaddr_region() local
106 …start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN… in mmu_ll_check_valid_ext_vaddr_region()
/hal_espressif-latest/components/esp_mm/
Desp_mmu_map.c74 intptr_t vaddr_end; //virtual address end of this block member
534 new_block->vaddr_end = mmu_ll_laddr_to_vaddr(new_block->laddr_end, MMU_VADDR_INSTRUCTION); in esp_mmu_map()
537 new_block->vaddr_end = mmu_ll_laddr_to_vaddr(new_block->laddr_end, MMU_VADDR_DATA); in esp_mmu_map()
656 (uint32_t) mem_block->vaddr_end, in esp_mmu_map_dump_mapped_blocks()
682 ESP_DRAM_LOGI(TAG, "block vaddr_end: 0x%x", mem_block->vaddr_end); in esp_mmu_map_dump_mapped_blocks_private()